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Showing 1 to 5 of 5 for “"compiler technique"”.

  1. Multiple-Pass Pipelining: Enhancing in-Order Microarchitectures to Out-of-Order Performance

    … simultaneous multithreading-like fashion. These techniques perform similarly to achievable out-of-order designs while comparing favorably in terms of power and complexity. An accompanying compiler technique and instruction marking further enhances the handling of miss latencies and reduces …

    uiuc Repository record for Multiple-Pass Pipelining: Enhancing in-Order Microarchitectures to Out-of-Order Performance (opens in a new tab)

  2. Parallel algorithms for verification of large systems

    … of a model into two steps. This well-known compiler technique simplifies the translation and still is very fast in practice.

    aachen Repository record for Parallel algorithms for verification of large systems (opens in a new tab)

  3. Prefetching for complex memory access patterns

    … contribute an automated software prefetching compiler technique to insert high-performance prefetches into program code to bring data into the cache early, achieving 1.3x geometric mean speedup on the most complex processors, and 2.7x on the simplest. I also provide an analysis of when and why …

    cambridge Repository record for Prefetching for complex memory access patterns (opens in a new tab)

  4. Improving Energy-efficiency in Sensor Networks by Raising Communication Throughput using STI

    … In addition to these, there are energy-aware compiler techniques, for example, those on optimization of code-generation techniques of compilers that advocate usage of instructions that consume the least energy, usage of compiler optimizations like loop unrolling and cloning, elimination of …

    ncsu Repository record for Improving Energy-efficiency in Sensor Networks by Raising Communication Throughput using STI (opens in a new tab)

  5. Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands

    … presents a novel decoupled latency tolerance technique for 1000-core data parallel processors. The approach focuses on developing instruction latency tolerance to improve performance for a single thread. The main idea behind the approach is to leverage the compiler to split the original thread …

    uiuc Repository record for Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands (opens in a new tab)