Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 22 for “"combinational circuits"”.
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The Design of Totally Self-Checking Combinational Circuits
Made available in DSpace on 2014-12-13T18:01:54Z (GMT). No. of bitstreams: 1 7709192.pdf: 4242354 bytes, checksum: 54c5c0fa8a81b23e6d6c8269be72649f (MD5) Previous issue date: 1976
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On the generation of test patterns for combinational circuits
… The faults are modeled as stuck-at faults for combinational circuits. To guarantee the completeness of the generated test set all redundant faults should be identified. For this purpose, the process of dynamic unique sensitization is implemented. This process studies the circuit for the …
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TENOR: an ATPG for transition faults in combinational circuits
Delay fault testing of high speed VLSI circuits is becoming increasingly important. This thesis presents an Automatic Test Pattern Generator (ATPG), called TENOR, for transition faults. Transition faults are a special case of gate delay faults. Test generation is based on the FAN algorithm. The …
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Low-Power-Driven Synthesis Algorithms for Sequential and Combinational Circuits
… results on each of our algorithm on a variety of combinational and sequential benchmark circuits.
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On detection of stuck-open faults using stuck-at test sets in CMOS combinational circuits
… complementary metal oxide semiconductor (CMOS) circuits. In general, test generation methods for detecting CMOS SOP faults are complex and time consuming due to the sequential behavior of faulty circuits. The majority of integrated circuit manufacturers still rely on stuck-at test sets to test …
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Syndrome signature in built-in self-testing of VLSI circuits.
… of the fault detection and location problem in combinational circuits. Classical testing of combinational circuits requires a list of fault-free responses of the circuit to the test set. For most practical circuits implemented today, the large storage requirement makes the test procedure very …
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Micro-operation perturbations in chip level fault modeling
… micro-operation perturbation faults. For small combinational circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various …
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A high-level approach to test generation for VLSI circuits
… problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator.
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High-Level Power Estimation
… (estimators) for activity, area, and delay for combinational circuits, thus making it possible to estimate power at the RT level. All of the above predictors work with a functional description of the design and avoid the time consuming translation of the RT description into a circuit-level …
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On improving parallel pattern single fault propagation for synchronous sequential circuits
… to be the most efficient for fault simulation of combinational circuits. Recently, PPSFP has been extended to synchronous sequential circuits [1]. The fault simulator called PARIS is the unique sequential circuit fault simulator based on PPSFP. In this thesis, four new heuristics are proposed to …
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Diagnostic test set evaluation and enhancement
… problem in the design and manufacturing of VLSI circuits. This thesis contributes to two important diagnosis topics, namely diagnostic fault simulation and diagnostic test pattern generation. First, a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and …
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Space compactor design for built-in self-testing of VLSI circuits from compact test sets using sequence characterization and failure probabilities.
… for built-in self-testing (BIST) of VLSI circuits using compact test sets with the primary objective of minimizing the storage required for the circuit under test (CUT) while maintaining fault coverage information is presented in this dissertation. The compaction technique utilizes the …
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On improving the performance of parallel fault simulation for synchronous sequential circuits
… fault simulation for synchronous sequential circuits have been investigated. Three heuristics were incorporated into a well known parallel fault simulator called PROOFS and the efficiency of the heuristics were measured in terms of the number of faults simulated in parallel, the number of …
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Fault simulation for supply current testing of bridging faults in CMOS circuits
… that considers bridging faults in CMOS circuits that are tested using supply current monitoring. The discussion is restricted to single fault detection in CMOS combinational circuits. A CMOS circuit is represented by a two-level hierarchy. At the higher level, the circuit is partitioned …
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Tools and Techniques for Evaluating Reliability Trade-offs for Nano-Architectures
… that can evaluate the reliability measures of combinational circuits, and can be used to analyze reliability-redundancy trade-offs for different defect-tolerant architectural configurations. In particular, we have developed two tools, one of which is based on probabilistic model checking and is …
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Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
… fault collapsing) for both nMOS and CMOS circuits including line stuck-at faults, transistor stuck short faults, and transistor stuck open faults are developed in the first part of the research. In the second part of the research, a new methodology is proposed for generating tests at the …
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Automatic back annotation of timing into VHDL behavioral models
… classified into four classes. The first class of circuits are combinational fanout free circuits in which the fanout of each process in the Process Model Graph is one. Combinational circuits in which outputs of the processes are fed in as input to more than one process are classified as Class 2 …
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Formal Verification Techniques for Reversible Circuits
… use of reversible logic instead of conventional combinational circuits. Theoretically, reversible circuits do not consume any power (or consume minimal power) when performing computations. This is achieved by avoiding information loss across the circuit. However, use of reversible circuits to …
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Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants
… been great strides made in the verification for combinational circuits, SEC still remains rather rudimentary. Without powerful SEC as a backbone, aggressive sequential synthesis and optimization are often avoided if the optimized design cannot be proved to be equivalent to the original one. In an …
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