Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 6 of 6 for “"clock network"”.
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Analysis and characterization of random skew and jitter in a novel clock network
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
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Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing
Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that …
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Recycling clock network energy in high-performance digital designs using on-chip DC-DC converters
… packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost …
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Modeling and reduction of dynamic power in field-programmable gate arrays
… activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of …
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Synthesis of Clock Trees with Useful Skew based on Sparse-Graph Algorithms
Computer-aided design (CAD) for very large scale integration (VLSI) involves
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Architecture and CAD techniques for optimizing FPGAs and reliability of integrated circuits.
… delays, which translates to 25% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced. With constant scaling of process technologies in the ultra deep sub-micron regime, chip design is becoming increasingly difficult due to process …