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Showing 1 to 14 of 14 for “"clock jitter"”.
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A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter
… ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of …
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A sampling jitter tolerant continuous-time pipeline ADC
A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling …
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Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology
… architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.
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On-Chip Voltage Controlled Oscillator for Clock Data Recovery Systems
As the clock rates of microprocessors keep increasing, high data rate input/output (IO) should be designed to realize their maximum benefit. However, designing robust, low power, high speed IO links is very challenging due to the increased transmission line loss, cross talk, and signal distortion …
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An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation
… in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses …
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A contribution to continuous-time quadrature bandpass sigma-delta modulators for low-IF receivers
… and the excess loop delay compensation scheme. Clock jitter severely reduces the modulator performance. The degradation of the SNR caused by clock jitter depends on the number of the output bit transitions. In order to reduce the jitter-induced noise, an optimized noise shaping transfer function …
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Front-end circuits for a photonic analog-to-digital converter
… limited at higher sampling rates due to sampling clock jitter, low-jitter mode-lock laser based photonic ADCs are starting to gain more attention. As well as low-jitter and high-linearity operation at very high speeds, photonic ADCs provide the opportunity to de-multiplex electrical signals to …
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CMOS Receiver Design for Optical Communications over the Data-Rate of 20 Gb/s
… is presented, and a new architecture for clock recovery is proposed for 50% higher clock rate. The TIA is based on a gm-boosted common-gate amplifier. The input-resistance is reduced by modifying a transistor at input stage to be diode-connected, and therefore lowers R-C time constant at …
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Radio frequency digital to analog converter
… (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (f), where k>l. …
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Techniques for high-performance digital frequency synthesis and phase control
… noise at this carrier frequency yields 204 fs of jitter (measured from 1 kHz to 40 MHz). In addition, a 3.2-Gb/s delay-locked loop (DLL) in a 0.18-[mu]m CMOS for chip-tochip communications is presented. By leveraging the fractional-N synthesizer technique, this architecture provides a …
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Predicting performance parameters of analog and mixed-signal circuits using built-in and built-off self test
… methodology for accurate prediction of aperture jitter using cost-effective loopback methodology. Aperture jitter is precisely separated from input and clock jitter as well as additive noise present in the DUT, by using an efficient loopback scheme. Hardware measurements were performed for all …
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Theory and implementation of digital bang-bang frequency synthesizers for high speed serial communications
… tolerance, and provided insights into the output clock jitter performance. The phase-plane based nonlinear analysis could not be usefully exploited in the presence of jitter on the reference clock and of thermal noise in the synthesizer’s internal blocks, so that a linearized model for the …
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Continuous-Time Delta-Sigma Modulators for Wireless Communication
… in loop delay. An RZ pulse, centered in the clock period, is used in the innermost feedback path which has the highest sensitivity to loop delay, while NRZ pulses are adopted in the outer feedback paths to reduce the sensitivity to clock jitter and lower the integrator slew rate requirements. …
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Continuous-Time Delta-Sigma Modulators for Ultra-Low-Power Radios
… The main focus is on power saving techniques and jitter insensitive solutions. Papers I and II present a CT DSM with dual switched-capacitor-resistor (DSCR) feedback used in the first DAC. This technique has been developed for the purpose of reducing the jitter sensitivity of the CT DSM while …