Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"charged device model (CDM)"”.
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Full chip modeling for predictive simulation of charged device model electrostatic discharge events
With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased usage of automated handlers is causing charged device model (CDM) ESD induced failures to become more prominent. Gate …
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Charged device model electrostatic discharge protection and test methods for integrated circuits
… (ESD). Specifically, this work focuses on charged device model (CDM) protection and test methods. In this work it is shown that the CDM robustness of an I/O can be increased by proper biasing of the gates during an ESD event. These gate bias networks are particularly useful because they do …
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Predictive transient circuit simulations of charged device model ESD events in system in package chips
This thesis focuses on obtaining circuit models to simulate the voltage stress experienced by the devices on integrated circuit components stressed by the charged device model (CDM) electro-static discharge (ESD) testers. The thesis presents a simple package modeling methodology that can be used to …
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Distributed electrostatic discharge protection for high-speed wireline receivers
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms
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Investigation of factors determining charged device model electrostatic discharge reliability of integrated circuits
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-08-01
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Charged device model electrostatic discharge failures in system on a chip and system in a package designs
… are inherently more robust than others during a CDM (Charged Device Model) event. Finally, the effects on the intensity of the CDM stress based on single-die or stacked-die packages will be compared.
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Design of reliable and energy-efficient high-speed interface circuits
DSpace SAF Submission Ingestion Package generated from Vireo submission #8656 on 2016-03-02 at 12:48:44