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Showing 1 to 3 of 3 for “"boundary scan"”.
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High level behavioural modelling of boundary scan architecture.
… enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the …
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Improved Signal Integrity in IEEE 1149.1 Boundary Scan Designs
… Setup or hold times violations may occur in a boundary scan chain using IEEE 1149.1 compliant devices. A practical study of the TDI-TDO scan data path has been conducted to show where problems may arise in relationship to a particular board topology and test system. This work points to …
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Design for pre-bond testability in 3D integrated circuits
… test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier …