Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 10 of 10 for “"body biasing"”.
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Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits
… leakage reduction methodology, leakage-aware body biasing, to overcome the shortcomings of a conventional Reverse Body Biasing (RBB) technique. The RBB technique has been used to reduce subthreshold leakage current. Therefore, this technique works well under subthreshold dominant region even …
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Subthreshold leakage control techniques for low power digital circuits
… that exploit dual threshold voltages and body biasing in order to reduce subthreshold leakage currents in both standby and active modes. To address standby leakage currents, a novel sleep transistor sizing methodology for MTCMOS circuits was developed and new "imbedded" dual V1 techniques …
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Characterization and mitigation of process variation in digital circuits and systems
… systematic components. Evaluation of adaptive body-biasing and voltage scaling as variation mitigation techniques proves voltage scaling is more effective in performance modification with reduced impact to idle power compared to body-biasing.
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Design Automation Flow for Voltage Adaptive Light Vth Hopping for Leakage Minimization in Sequential Circuits
… techniques like Power Gating (PG) and Reverse Body Biasing (RBB) being the primary candidates for RALC, PG is found to give better leakage savings than RBB and hence is a popular technique in the industry.</p><p> Comparing PG and RBB techniques, RBB has less overhead and average leakage …
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EFFICIENT VOLTAGE REGULATION USING SWITCHED CAPACITOR DC/DC CONVERTER FROM BATTERY AND ENERGY HARVESTING POWER SOURCES
… capacitors, local gate driving and adaptive body biasing to reduce the power loss in monolithic SC converter implementation. To control the SC power stage for accurate regulation and fast transient response, a control scheme named adaptive gain/pulse control is developed. The research also …
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Study and development of low power consumption SRAMs on 28 nm FD-SOI CMOS process
… (SPW) structure in combination with reverse-body-biasing (RBB) technique were used to achieve a better balance between P-type and N-type transistors. As a result, we developed a 128 kB SRAM cache, whose post-layout simulations show that the circuit consumes an average energy per operation of …
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Energy-efficient smart embedded memory design for IoT and AI
… in a modern 28nm FDSOI process. Dynamic forward body-biasing (DFBB) is used to improve the write operation, and reduce the minimum Vdd to 0.34V, even with 6T bit-cells. A new layout technique is proposed for the array, to reduce the energy overhead of DFBB and decrease the unwanted bit-line …
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Energy-efficient SRAM design in 28nm FDSOI Technology
… (Vdd,min) is achieved by using dynamic forward body-biasing (FBB) on the NMOS devices of the bit-cell. The overhead of dynamic FBB is reduced by implementing it row-wise. Layout modifications are proposed to share the body terminals (n-wells) horizontally, along a row. Further savings in …
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Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation
… exploration. Techniques such as device sizing, body biasing, stacking transistors, dual threshold gates, multi threshold synthesis, pipelining, and loop unfolding, are explored and applied to the designs. The designs are synthesized in a 65 nm CMOS technology with low-power and three threshold …