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A timeshared, runtime reconfigurable hardware co-processing architecture

Gelb, Benjamin SMassachusetts Institute of Technology2009

… bitparse and bitrender, to demonstrate the bitstream relocation technique. Further, we present a functional microprocessor system coupled with a runtime reprogramable peripheral synthesized on a Xilinx Virtex-5 FPGA and discuss its performance implications.

mit Repository record for A timeshared, runtime reconfigurable hardware co-processing architecture (opens in a new tab)

Accelerated Frame Data Relocation on Xilinx Field Programmable Gate Array

Kallam, Ramachandra

utahstate Repository record for Accelerated Frame Data Relocation on Xilinx Field Programmable Gate Array (opens in a new tab)

Improved Framework for Fast and Efficient Memory-Based Frame Data Reconfiguration for Multi-Row Spanning Designs on Field Programmable Gate Arrays

Sreeram, Rohan

utahstate Repository record for Improved Framework for Fast and Efficient Memory-Based Frame Data Reconfiguration for Multi-Row Spanning Designs on Field Programmable Gate Arrays (opens in a new tab)