Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 12 of 12 for “"bit flips"”.
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Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power
… the soft error rate by 33% and 31.5% for double bit flips and triple bit flips, respectively, compared to SVmap, and by 52.9% and 50.3% for double bit flips and triple bit flips, respectively, compared to Emap.
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The Optimal Error Resilience of Interactive Communication Over Binary Channels
… of such a protocol in the face of adversarial bit flips or erasures. While the optimal error resilience of such a protocol over a large alphabet is well understood, the situation over the binary alphabet has remained open. Over the binary alphabet, there has remained a substantial gap in error …
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Developing a multi-level fault injection environment
… Such errors are termed "soft errors". Bit flips in the design are good way to model these soft-errors. These bit-flips due to soft errors are random and transient in a design, making their analysis more difficult than simple stuck-at faults. Interestingly only a few of the flops which …
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Extensible Platforms for Bosonic Quantum Error Correction
… cavity controlled via fixedfrequency transmon qubits [1, 2, 3, 4, 5, 6]. To date, all previous demonstrations have been limited by bit-flips in the transmon control qubit (with typical T1 lifetimes on the order of 100 microseconds), resulting in logical lifetimes that are upper-bounded by …
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Physical Layer Data Integrity Attacks and Defenses in Cyber-Physical Systems
… research, the use of IEMI to induce controlled bit flips in widely used serial digital communication protocols is examined. In contrast to state-of-the-art IEMI attacks that use a narrow-band sinusoid as an attack signal, a complex, wideband, rectangular waveform is designed to improve the …
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Machine Learning Model Watermarking through DRAM PUFs
… fingerprints, and DRAMs have been shown to exhibit inherent PUF behavior. One way to generate a PUF from DRAM is by disabling the DRAM refresh mechanism, which causes bit-flips in the stored charge. In my work, a machine learning model is trained on a PUF-enabled DRAM platform where the model …
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Integrating physical unclonable functions from novel nanomaterials, circuit elements, and memory technologies into future hardware architectures
… such as intentional timing manipulation, induced bit flips through row hammering, and variations in supply voltage are examined. These resulting bit flips can be exploited as PUF responses. Additionally, transforming raw PUF responses into cryptographically usable keys and integrating specific …
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Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach
… we, for the first time, identified gate-level bit-flip patterns from a SPICE level high-voltage event. Our experimental results show that the extent of register value corruption can be single-bit or widespread, and the bit flips manifested can affect the system in multiple ways. We also …
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Towards Secure Machine Learning Acceleration: Threats and Defenses Across Algorithms, Architecture, and Circuits
… an algorithm to identify the most vulnerable bits among the model parameters of a sparse DNN. SparseBFA shows that a victim DNN is highly susceptible to a few bit flips in the coordinates of sparse weight matrices, less than 0.00005% of the total memory footprint for its parameters. Second, …
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Democratizing error-efficient computing
… a wide variety of sources -- from unintentional bit flips in devices to deliberate approximations and malicious attacks. Future systems must be built to extract maximum computational efficiency while operating with heterogeneous sources of errors. The paradigm of Error-Efficient Computing offers …
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Detection of ESD-induced soft errors
IEC-61000-4-2 compliant ESD discharges are performed on a microcontroller. The effect of ESD-induced noise on a digital system having a workload is examined. UART interface present on-chip is used for memory and register readout. Hardware voltage monitors developed previously are included in the …
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Characterizing Retention behavior of DDR4 SoDIMM
… immediate information for processing needs. Each bit in a DRAM memory module is implemented with a tiny capacitor and a transistor. Since the capacitors are prone to charge leakage, each bit must be frequently rewritten with its old value. A dedicated memory controller handles the periodic …