Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 11 of 11 for “"behavioral synthesis"”.
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Constraint Driven Behavioral Synthesis
… for applying this model to computer architecture behavioral synthesis is also described. In behavioral synthesis, an abstract description of a system and a set of imposed constraints are used to design a register-transfer level implementation of the desired machine. Several runs of the system are …
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Timing Analysis and Behavioral Synthesis with Process Variation
… paths. The second piece of work extends the behavioral synthesis task of binding to be variation-aware through our algorithm FastYield. FastYield off ers several contributions to the field of statistical design. First, it presents the unit correlation model, a model that can be used to model …
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A framework for behavioral synthesis from partial design structures
This thesis describes a new approach to behavioral synthesis which allows for designer interaction and gradual motion towards automatic synthesis. Issues in design models, input languages, internal representation and structural component characterization have been examined in detail to overcome …
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A system for microarchitecture and logic optimization
… methods has resulted in the design of numerous behavioral synthesis and logic synthesis tools. This thesis spans two levels of the design process by examining optimization at both the register-transfer level and at the logic level. More specifically, this thesis addresses the following two …
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BETA: Behavioral Testability Analyzer and its applications to high-level test generation and synthesis for testability
In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test …
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A performance driven approach for hardware synthesis of guarded atomic actions
… (for example, Verilog), or the language and synthesis methodology is so high-level that the designer's micro-architectural ingenuity is lost in the design process. This results in circuits that oftentimes do not match the designer's expectations (for example, C-based behavioral synthesis). …
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Temperature and Interconnect Aware Unified Physical and High Level Synthesis
… development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power consumption, …
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High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design
… (ii) How do we enable power aware High Level Synthesis to automatically synthesize RTL implementation from ESL? This dissertation distinguishes itself by addressing the following two issues: (i) Since power/energy consumption of electronic systems largely depends on implementation details, and …
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High-Level Resource Binding and Allocation for Power and Performance Optimization
… are challenges to circuit designers. High-level synthesis has been touted as a solution to these problems, as it can both significantly reduce the number of man hours required for a circuit design, and offer greater opportunities for optimization of design goals, by raising the level of …