Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 76 for “"Wafer Scale"”.
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Achieving wafer scale synthesis of molybdenum ditelluride through precursor engineering
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms
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Task flow: A novel approach to fine-grain wafer-scale parallel computing
This thesis introduces a parallel computer architecture known as task flow. Simple replicated cells contain both memory packets and processing logic. Each memory packet contains a data field, the next instruction, and a link. Transmission packets flow between memory packets to communicate …
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High performance MoS₂ transistors based on wafer-scale low-temperature MOCVD synthesis
… potential in realizing 3D integration. However, wafer-scale growth of high-quality, continuous 2D materials thin film with BEOL compatible temperature (<400°C) and good uniformity has always been difficult to realize. To achieve low contact resistance to these materials is also very challenging …
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Electron beam techniques for testing and restructuring of wafer-scale integrated circuits
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1981
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Wafer-scale integrated active silicon photonics for manipulation and conversion of light
… by inheriting the cost-effective, very large scale integration capabilities from complementary metal-oxide-semiconductor (CMOS) process. The compatibility with CMOS also merges the electronics and photonics world in a single platform. While electronics are key for computations, photonics are …
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CMOS-Compatible Wafer-Scale Synthesis and Rapid Characterization of Two-Dimensional Transition Metal Dichalcogenides
… manufacturing demands CMOS-compatible, wafer-scale growth and conventional CVD methods often exceed thermal budgets and introduce contaminants, while achieving uniform, defect-free monolayers remain difficult. This thesis presents in-depth discussion on low-temperature MOCVD system …
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Control of wafer-scale non-uniformity in chemical-mechanical planarization by face-up polishing
… a key process in the manufacture of ultra-large-scale-integrated (ULSI) semiconductor devices. A major concern in CMP is non-uniform planarization, or polishing, at the wafer-scale - primarily as interconnect metal dishing and dielectric erosion. In conventional face-down CMP, the pad is much …
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LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS
… covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin …
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A feature-to-wafer-scale model of etch-rate non-uniformity in deep reactive ion etching/
… etch rate variation in DRIE by integrating wafer- and feature-scale nonuniformity models that are grounded on an ion-neutral synergy model for etch rate. Our method focuses on diffusive transport and local depletion of Fluorine radicals above the wafer surface to facilitate integration of …
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Layer-by-Layer Single-crystal Two-dimensional Material Growth by Geometric Confinement
… growth, 2) maintaining single crystallinity at wafer-scale, and 3) inevitable transfer-process to fabricate heterostructure for various next-generation applications such as spintronics, valleytronics, and optoelectronics. This thesis introduces a confined-growth technique that can overcome the …
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Development of Transition Metal Dichalcogenide Memristive Materials and Devices for Neuromorphic Systems
… mimics synaptic functions. However, reproducible wafer-scale deposition and reliable integration into memristive devices remain key challenges. This work investigates the three representative TMDCs molybdenum disulfide, hafnium disulfide, and tungsten disulfide, selected to reflect contrasts in …
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Single crystal silicon as a macro-world structural material : application to compact, lightweight high pressure vessels
… crystal silicon (Si) for high-strength macro-scale application and determines its practical advantages when compared to conventional approaches. The major contributions of this thesis includes evaluation of wafer-scale silicon for macro-world applications, identification of cellular pressure …
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Analysis of slurry flow in chemical-mechanical polishing
… is non-uniform polishing rate at the die and wafer scales. In this thesis, an innovative CMP machine configuration is proposed to minimize wafer-scale non-uniformity. The new face-up machine lowers wafer-scale non-uniformity by minimizing over-polishing of any particular area. The thesis …
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Wafer bonding : mechanics-based models and experiments
Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the process is currently employed in applications such as these, a lack of …
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Novel nanomanufacturing methods for bottom-up III-V nanowires and van der Waals epitaxy of monolayer MoS2
… MoS2, obtaining a single-crystal phase with a wafer-scale uniform monolayer is needed in order for the material to be mass fabricated. Although wafer scale monolayer MoS2 has successfully been grown, it contained a high density of grain boundaries which would cause non-uniform performance when …
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Atomic-scale assessment of graphene-substrate interactions, grain boundaries, and materials for heterostructures
… nanoelectronic devices, primarily defects from wafer-scale graphene synthesis, graphene-substrate interactions, and growth of graphene’s insulating analog, hexagonal boron nitride (h-BN). These experimental studies are fundamental in nature, but they highlight parameters relevant to …
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Array-based planar nanowire high electron mobility transistor
… fabricating bottom-up NW-FETs and circuits in wafer-scale is still in question. The main challenges include: controllability of NW position, uniformity of NW electrical property, and compatibility with planar processing. In this thesis research, a bottom-up planar-NW high electron mobility …
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Network-on-chip design for a chiplet-based waferscale processor
… architectural changes to enable performance to scale acceptably. One significant architectural change is the shift from bus and crossbar based processor interconnections to networks-on-chip (NoCs). This thesis details the design of an NoC to enable a shared memory architecture in a chiplet-based …
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Nonplanar Nanofabrication via Interface Engineering
… achieve. Our approach, which builds on standard, wafer-scale, and conventionally-compatible techniques, is versatile, tunable, and compatible with diverse materials. As a result, the technique opens up new opportunities for applications such as miniaturized nanoelectromechanical devices, including …
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Planar nanowire high electron mobility transistor and down-scaling of planar nanowire
… done for the realization of high-quality down-scaled planar GaAs NWs with widths as small as 35 nm. With further development of our planar NW technology, wafer-scale low-power and high-speed VLSI circuits involving 3D planar NW channel from the bottom-up is promising.
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