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Showing 1 to 20 of 49 for “"Voltage Scaling"”.

  1. Self-tuning dynamic voltage scaling techniques for processor design

    The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS …

    texas Repository record for Self-tuning dynamic voltage scaling techniques for processor design (opens in a new tab)

  2. Assessing Approximate Arithmetic Designs in the presence of Process Variations and Voltage Scaling

    … increasing from 6psec to 12psec, and when the voltage is scaled to Near-Threshold-Voltage (NTV) levels sigma increases by up to 5psec. Approximate Arithmetic Units were not affected greatly by the change in distribution of the thickness of the gate oxide. Even when considering the 3-sigma …

    ucf

  3. Power Management Schemes for Ultra Low Power Biomedical Devices

    … due to the rapid transistor technology scaling and increased circuit complexity. Motivated by the ultra low power requirements of emerging implantable and wearable biomedical devices, novel power management schemes are presented in this thesis to increase device run-time. The schemes …

    vu-aus Repository record for Power Management Schemes for Ultra Low Power Biomedical Devices (opens in a new tab)

  4. A zero-crossing based pipelined analog-to-digital converter with supply voltage scalibility

    … technique enables energy efficient operation and voltage scaling. Supply voltage scaling based on the required sampling frequency and resolution provides high energy efficiency over a wide range of sampling frequencies and resolutions. A two phase charge transfer scheme (course charge transfer and …

    mit Repository record for A zero-crossing based pipelined analog-to-digital converter with supply voltage scalibility (opens in a new tab)

  5. Heteroepitaxial Ge on Si via High-Bandgap III-V Buffers for Low-Power Electronic Applications

    Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing …

    vt Repository record for Heteroepitaxial Ge on Si via High-Bandgap III-V Buffers for Low-Power Electronic Applications (opens in a new tab)

  6. Effect of MOSFET threshold voltage variation on high-performance circuits

    … industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. …

    mit Repository record for Effect of MOSFET threshold voltage variation on high-performance circuits (opens in a new tab)

  7. Characterization and mitigation of process variation in digital circuits and systems

    … threatens to negate a whole generation of scaling in advanced process technologies due to performance and power spreads of greater than 30-50%. Mitigating this impact requires a thorough understanding of the variation sources, magnitudes and spatial components at the device, circuit and …

    mit Repository record for Characterization and mitigation of process variation in digital circuits and systems (opens in a new tab)

  8. Parallel algorithms and architectures for low power video decoding

    Parallelism coupled with voltage scaling is an effective approach to achieve high processing performance with low power consumption. This thesis presents parallel architectures and algorithms designed to deliver the power and performance required for current and next generation video coding. Coding …

    mit Repository record for Parallel algorithms and architectures for low power video decoding (opens in a new tab)

  9. Investigation into low power and reliable system-on-chip design

    … system-level design techniques for MPSoCs with voltage scaling enabled processors highlighting the trade-offs between performance, power consumption and reliability.<br/><br/>An important aspect in the system-level design is to validate reliability in the presence of soft errors through …

    soton Repository record for Investigation into low power and reliable system-on-chip design (opens in a new tab)

  10. Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency

    … maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing …

    arkansas Repository record for Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency (opens in a new tab)

  11. Design Techniques for Frequency Synthesizers in Highly Scaled CMOS Technologies

    … conventional analog circuits, CMOS technology scaling, on the other hand, has also opened up new opportunities for analog and mixed-mode circuit designs to mitigate design challenges by the speed improvement and the high density of the nanometer devices. Phase-locked-loop-based frequency …

    columbia-diss Repository record for Design Techniques for Frequency Synthesizers in Highly Scaled CMOS Technologies (opens in a new tab)

  12. Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control

    This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. …

    vt Repository record for Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control (opens in a new tab)

  13. Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability

    … platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced control of the performance and energy efficiency. Datapath control logic with NULL Cycle Reduction (NCR) and arbitration network are …

    arkansas Repository record for Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability (opens in a new tab)

  14. Exploiting application level error resilience via deferred execution

    … with switching between the modes, typically via voltage scaling, which may require hundreds to thousands of cycles to transition between levels. We propose a novel execution model for single-core architectures that reduces total switching by deferring execution of instructions requiring mode …

    uiuc Repository record for Exploiting application level error resilience via deferred execution (opens in a new tab)

  15. Multipass communication systems for tiled processor architectures

    … can also be leveraged to reduce power through voltage scaling and/or the use of higher Vt devices. The characteristics of general-purpose parallel processors for communications processing are explored, as well as the applicability of specific parallel designs to communications processing.

    mit Repository record for Multipass communication systems for tiled processor architectures (opens in a new tab)

  16. Evaluation and Analysis of NULL Convention Logic Circuits

    … technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization of this design paradigm. </p> <p>This dissertation evaluates the nominal dynamic energy, voltage-scaled dynamic energy, and static power consumption of NCL across variations in …

    arkansas Repository record for Evaluation and Analysis of NULL Convention Logic Circuits (opens in a new tab)

  17. 0.3V biopotential sensor interface for stress monitoring

    … require long operation lifetime. Exploiting low-voltage techniques in analog design can enable further power savings, which has not been explored much. However, for conventional analog-front-end (AFE) topologies, voltage scaling could potentially bring several limitations to the important …

    mit Repository record for 0.3V biopotential sensor interface for stress monitoring (opens in a new tab)

  18. Delay Line Based Adc And High Frequency Pulse Generation In Electrical Lc Latices

    … (ADC) in time-domain resolutions. With the down scaling of the minimal feature size of modern submicron CMOS technologies, time-to-digital conversion (TDC) is found very useful in many applications as well as analog-todigital converters. This is the case when it is profitable to replace badly …

    cornell Repository record for Delay Line Based Adc And High Frequency Pulse Generation In Electrical Lc Latices (opens in a new tab)

  19. Managing Many-Core Aging

    Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling. In future designs, the majority of the cores will necessarily have to be dormant at …

    uiuc Repository record for Managing Many-Core Aging (opens in a new tab)

  20. Low power data-dependent transform video and still image coding

    … the DCT computation context along with standard voltage scaling techniques such as pipelining and parallelism. The first method reduces the bitwidth of arithmetic operations in the presence of data spatial correlation. The second method trades off power dissipation and image compression quality …

    mit Repository record for Low power data-dependent transform video and still image coding (opens in a new tab)

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