Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Vertical Interconnects"”.
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Multi-connection vias for printed circuit boards
… signal impedance. Conventional multi-layer vertical interconnects, which connect between board layers, are not impedance matched to the in-plane signal traces. Multi-connection vias, developed in this thesis, provide a method for matching the impedance of vertical and in-plane features by …
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Design Automation and Evaluation Of Emerging 3D – IC Technology Using Stacked Horizontal Nanowires
… pre-fabricated dies or wafers are stacked in a vertical manner. The existing 3-D ICs can be categorized into multilithic and monolithic 3-D integration approaches. However, both existing approaches provide only incremental density benefits, and face reliability, thermal management, large area …
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Designing High-Performance Microprocessors in 3-Dimensional Integration Technology
… technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, thus reducing …
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Three-Dimensional Heterogeneous Integration for RF/Microwave Applications
… processing. In such systems, heterogeneous vertical integration, in which circuits in different technologies can be stacked on top of each other within the system architecture, can reduce the overall system size and power consumption. Chip stacking also enables optimally-performing …
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Modeling and simulation for signal and power integrity of electronic packages
… circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the …
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
… continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active …