Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 5 of 5 for “"Verilator"”.
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Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution
… cores, ASH is gmean 1,485× faster than 1-core Verilator, and it is 32× faster than Verilator on a server CPU with 32 complex cores while using 3× less area.
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Task Scheduling Techniques to Accelerate RTL Simulation
… cores, ASH is gmean 1,485× faster than 1-core Verilator, and it is 32× faster than Verilator on a server CPU with 32 complex cores while using 3× less area.
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Brute-force resistant Pointer-Authentication using RISC-V co-processor
… LLVM pass. Experiments are conducted on both a Verilator-based Rocket Chip simulation and a Xilinx VCU118 FPGA implementation. Results indicate that PAC instrumentation incurred a performance overhead of 1.3% to 5.8%, with average slowdowns consistently below 6% across platforms. These findings …
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Increasing Branch Coverage with Dual Metric RTL Test Generation
… RTL source to a C++ equivalent using a modified Verilator, which also automatically creates mutants and the corresponding mutated C++ design, based on arithmetic, logical and relational operators during conversion. With the help of extracted Data Dependency and Control Flow Graphs, in every …
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Guiding RTL Test Generation Using Relevant Potential Invariants
In this thesis, we propose to use relevant potential invariants in a simulation-based swarmintelligence-based test generation technique to generate relevant test vectors for design validation at the Register Transfer Level (RTL). Providing useful guidance to the test generator for such techniques …