Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 20 for “"VLIW"”.
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Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren
… skalierbarer Very-Long-Instruction-Word (VLIW)-Prozessoren eignen sich insbesondere für Anwendungsszenarien, in denen eine hohe Ressourceneffizienz gefordert ist. Diese Arbeit dokumentiert die Entwurfsraumexploration einer skalierbaren und ressourceneffizienten VLIW-Architektur – dem …
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Data preload for superscalar and VLIW processors
… techniques, such as pipelining, superscalar, and VLIW, have dramatically decreased the average number of clock cycles per instruction. As a result, each execution cycle has become more significant to overall system performance. To maximize the effectiveness of each cycle, one must expose …
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Efficient Binary Field Multiplication on a VLIW DSP
… ARM Cortex A8 to a specialized C64x+ VLIW DSP, we are able to exploit the XOR-Multiply instruction and the inherent parallelism of the DSP. The proposed multiplication utilizes Multi-Precision Binary Polynomial Multiplication with Unbalanced Exponent Modular Reduction. The resulting …
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Code compaction and parallelization for VLIW/DSP chip architectures
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
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A flexible compilation infrastructure for VLIW and SIMD architectures
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
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Convergent scheduling : a flexible and extensible scheduling framework for clustered VLIW architectures
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2003.
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Design And Analysis Of Time-Predicatable Single-Core And Multi-Core Processors
… Therefore, the time predictability of VLIW (Very Long Instruction Word) processors and its compiler support is studied. The impediments to time predictability for VLIW processors are analyzed and compiler-based techniques to address these problems with minimal modifications to the VLIW …
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Memory disambiguation to facilitate instruction-level parallelism compilation
… make effective use of wide-issue superscalar and VLIW processor resources, the compiler must perform aggressive low-level code optimization and scheduling. However, ambiguous memory dependences can significantly limit the compiler's ability to expose ILP. To overcome the problem of ambiguous …
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An instruction scheduling algorithm for communication-constrained microprocessors
… algorithm designed for communication-constrained VLIW-style machines. The algorithm was implemented in a retargetable compiler system for testing on a variety a different machine configurations. The algorithm performed acceptably well for machines with full communication, but did not perform up to …
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TIME-PREDICTABLE FAST MEMORIES: CACHES VS. SCRATCHPAD MEMORIES
… memory (SPM) based architectures for both VLIW (Very Long InstructionWord) based single-core and multicore processors. First, this dissertation proposes a time predictable two-level SPM based architecture for VLIW based single-core processors, and an ILP (Integer Linear Programming) based …
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Reducing exception management overhead with software restart markers
… quantities of programmer-visible state, such as VLIW or vector processors. As architects increasingly rely on parallel architectures to achieve higher performance, the problem of exception handling is becoming critical. In this thesis, I present software restart markers as the foundation of an …
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Enhancing instruction-level parallelism through compiler-controlled speculation
… non-numeric programs (1) (2) (3). An effective VLIW or superscalar processor must optimize and schedule instructions across basic block boundaries to achieve higher performance. An effective structure for ILP compilation is the superblock (4). The formation and optimization of superblocks …
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Performance evaluation of vector machine architectures
… horizontal superscalar architectures, e.g., VLIW and polycyclic architectures, provide a more balanced performance across a wider range of scientific workloads than do vector machines. The purpose of this research is to study the performance of register-register vector processors, such as …
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Cluster assignment and instruction scheduling for partitioned register-set machines
… Many of their successful designs such as VLIW and superscalar machines use multiple functional units trying to exploit instruction level parallelism in computer programs. As the number of functional units rises, another hardware constraint enters the picture---the number of register-file …
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Evaluating the Scalability of SDF Single-chip Multiprocessor Architecture Using Automatically Parallelizing Code
… of CPU design. Compared with superscalar, VLIW (very long instruction word), and SMT (simultaneous multithreading), the experiment results show that for application with very little parallelism SDF is comparable to other architectures, for applications with large amounts of parallelism SDF …
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Approximation of CPU code using neural networks
… tools such as very long instruction word (VLIW) compilers, CUDA, and logic synthesis have made it easier than ever for even novice programmers to leverage the increased efficiency of DSP cores, GPUs, and FPGAs using specialized high-level programming languages for those devices. However, …
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Compiler Optimization Techniques for Scheduling and Reducing Overhead
… as opposed to caches, etc. With the advent of VLIW processors, the exploitation of fine-grain instruction-level parallelism has become a major challenge to optimizing compilers. Fine-grain scheduling of inner loops has received a lot of attention, little work has been done in the area of …
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Vector processor virtualization: distributed memory hierarchy and simultaneous multithreading
… for such applications. Superscalar and VLIW (Very Long Instruction Word) processors, along with SIMD (Single-Instruction Multiple-Data) and vector processor (VP) accelerators, are among the available options for designers to accomplish their desired requirements. On the other hand, these …
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Combining FPGA prototyping and high-level simulation approaches for Design Space Exploration of MPSoCs
… application binary code, compiled for a custom VLIW ASIP architecture, that is transformed into code executable on a different configuration. This allows to prototype a whole set of ASIP solutions after one single FPGA implementation flow, mitigating the afore-mentioned overhead.A short overview …