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Showing 1 to 16 of 16 for “"VHDL models"”.
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Automatic verification of VHDL models
… A scheme for the automatic verification of VHDL (VHSIC Hardware Description Language) models has been proposed. In the proposed scheme the specifications for the hardware system, i.e.,the timing constraints and relations between input and output signals are described by the designer in …
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A graphical representation for VHDL models
… a graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the …
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Development of Web-Based Educational Modules for Testing VHDL Models of Digital Systems
… and maintenance personnel on how they can use VHDL to design and maintain digital systems. The educational modules provide extensive information on VHDL modeling and testing styles and standards at various abstraction levels. The Sobel edge detector model was chosen as an example to explain the …
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Development of Web-Based Educational Modules for Developing VHDL Models of Digital Systems
Hardware description languages (HDLs) such as VHDL have made it possible for circuit and board designs to be done without resorting to paper, allowing computers to manage the design database and automate the translation between various representations of the system. Although VHDL modeling can …
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An efficiency rating tool for process-level VHDL behavioral models
Due to the great complexity of VHDL models that are created today, the amount of processing time required to simulate these models and the amount of labor required to develop these models have become critical issues. The amount of processing time required to simulate a model can be directly …
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Simulation of large-scale system-level models
… efficient simulation of large-scale system-level VHDL models is analyzed. The system-level models chosen for the investigation are multicomputer networks, which are scalable up to thousands of processing nodes. Initially, a classification of parallel processing architectures is presented along …
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Timing distribution in VHDL behavioral models
… enables the use of imbedded timing in behavioral VHDL models, thereby providing accurate VHDL descriptions. Due to this modeling methodology, the end-to-end delays for all the paths in the digital device are made available. Also, due to the Register Transfer Level (RTL) of abstraction, which is …
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Model Development, Synthesis and Validation Using the Modeler's Assistant
… tool which aids in the rapid development of VHDL models. The tool provides modeling, test bench generation, simulation, synthesis and validation features. The 'Process Model graph' which has representations for the concurrent processes is used as the basis for Modeler's Assistant. Test …
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Development of VHDL behavioral models with back annotated timing
… for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral …
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Modeling SAR signals and sensors using VHDL
… data. If the signal processor is modeled in VHDL then the sequence of sensor data will be applied to the model in a VHDL test bench. Generation of the sensor data and sensor models for VHDL testbenches is a labor intensive task which cannot be performed manually. This thesis concentrates on …
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A test generation system for behaviorally modeled digital circuits
… presents an approach to generating tests from a VHDL behavioral model. The tests can be used to thoroughly exercise the VHDL model and detect the faults in the equivalent gate level circuit of the model. The VHDL model is developed with the help of the Modeler's Assistant and represented as a …
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Natural language interface to a VHDL modeling tool
… describes a Natural Language (NL) interface to a VHDL modeling tool called the Modeler's Assistant. The primary motivation for the interface developed in this research work is to permit VLSI modelers who are not proficient in VHDL to rapidly produce correct VHDL models from manufacturer's …
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Hardware implementation of a low-power two-dimensional discrete cosine transform
… architectural design, development of the C and VHDL models, verification methods, synthesis operations, static timing analysis, design for test compliance, power analysis, and performance comparisons for the development of the core. The work has been completed in the ASIC Digital Cores I …
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Automated Testbench Generation for Communication Systems
… methods to generate testbenches for VHDL models of communication systems. To illustrate the methods, a VHDL model was constructed for the speech-coding channel of the Global System for Mobile Communication (GSM). GSM is the Pan-European digital mobile telephony standard specified by …
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A test plan driven test bench generation system
Testing and verification of large DSP models is a laborious and time consuming task. Test benches provide a platform for testing VHDL models. Development of good test benches is very critical in reducing the time, manpower and costs involved in testing of such models. Sometimes the development of …
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System level simulation of digital designs : a case study
… Circuit Hardware Description Language (VHDL) is a hardware description language that is gaining increasing popularity among digital designers in South Africa, as it is both a synthesis and simulation language. Many designers make use of the language's synthesis ability but hardly tap …