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Showing 1 to 18 of 18 for “"Timing Model"”.

  1. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization

    <p>The modeling of an individual gate and the optimization of circuit performance has long been a critical issue in the VLSI industry. In this work, we first study of the gate sizing problem for today's industrial designs, and explore the contributions and limitations of all the existing …

    syracuse-diss Repository record for Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization (opens in a new tab)

  2. Forecasting Event Ticket Sales

    … held at a large entertainment venue to develop a model that forecasts ticket sales. Data from thirteen different events are used, and the model chosen is a timing model which draws from two Weibull segments and clusters events into 2 separate groups. The paper provides some background into why …

    penn Repository record for Forecasting Event Ticket Sales (opens in a new tab)

  3. Testing capital structure theories : Evidence from REITs

    … theory, the pecking order theory and the market timing theory are three competing theories of capital structure that have been widely examined in finance literature. But empirical tests of REITs capital structure were limited.This study employs a partial adjustment model of Fama and French (2002) …

    nus Repository record for Testing capital structure theories : Evidence from REITs (opens in a new tab)

  4. An efficient test generation algorithm for behavioral descriptions of digital devices

    … signal assignment statements. The fault model based on previous research includes micro-operation and control faults. The test generation algorithm uses artificial intelligence techniques of goal trees and rule databases and it can make use of human understanding of the device model to …

    vt Repository record for An efficient test generation algorithm for behavioral descriptions of digital devices (opens in a new tab)

  5. Functional and timing models for a programmable hardware accelerator

    … class of problems more efficiently. Performance models are useful for evaluating the performance of different applications and design alternatives. This project develops a functional model for this hardware accelerator as well as a simple timing model to allow for examination of the performance …

    mit Repository record for Functional and timing models for a programmable hardware accelerator (opens in a new tab)

  6. An automatic test generation method for chip-level circuit descriptions

    … of VHDL, with a simplified period-oriented timing model. The fault model, based on previous research, includes micro-operation and control statement faults. The test method uses path-tracing, working directly from the circuit description, not a derived graph or table. Artificial intelligence …

    vt Repository record for An automatic test generation method for chip-level circuit descriptions (opens in a new tab)

  7. Eavesdropping risks of the DisplayPort video interface

    … The attack starts by recovering scrambler timing parameters and synthesising a replica of the scrambler synchronised with the target. This replica is then used to build templates for each of the expected colours, and to identify pixel colours from short-term cross-correlation between the …

    cambridge Repository record for Eavesdropping risks of the DisplayPort video interface (opens in a new tab)

  8. Routing and scheduling models for robust allocation of slack

    … unavoidable. Most conventional scheduling models, however, ignore the presence of uncertainties in actual operations in order to limit the complexity of the problem. This leads to schedules that are prone to delays and disruptions. As a result, there has been wide interest recently in …

    mit Repository record for Routing and scheduling models for robust allocation of slack (opens in a new tab)

  9. Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities

    … work on 2-D cell characterization shows that the timing variations can be characterized by the timing model. However, as regular design rules become necessary in sub-45 nm node circuit design, 1-D design has shown its advantages and has drawn intensive research interest. The circuit performance of …

    uiuc Repository record for Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities (opens in a new tab)

  10. VLSI Physical Design for Manufacturability and Reliability

    … 4. Its applications, such as maze routing, timing analysis and buffer insertion, are discussed. Proposed algorithm can handle an arbitrary function of mean and variance of path weight instead of convex constraint needed for existing algorithms. In Chapter 5, buffer insertion under process …

    uiuc Repository record for VLSI Physical Design for Manufacturability and Reliability (opens in a new tab)

  11. Processing Speed in Children: Examination of the Structure in Middle Childhood and its Impact on Reading

    … childhood by comparing five theoretically driven models of PS. The models consisted of two conceptual models (a unitary model, a complexity model) and three methodological models (a stimulus material model, an output modality model, and a timing modality model). A second aim was to evaluate the …

    houston Repository record for Processing Speed in Children: Examination of the Structure in Middle Childhood and its Impact on Reading (opens in a new tab)

  12. On the Characterization of Library Cells

    … The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for …

    vt Repository record for On the Characterization of Library Cells (opens in a new tab)

  13. A verified compiler for Handel-C

    … sound reasoning framework in which the a formal model of the source Handel-C program can be embedded and refined into a formal abstraction of the target hardware. As the algebraic rules used to compile the program are proven to preserve the semantics, the correctness of the entire compilation …

    whiterose Repository record for A verified compiler for Handel-C (opens in a new tab)

  14. Style anomalies on the Toronto Stock Exchange : a univariate, multivariate, style timing and portfolio sorting analysis

    … inconsistencies in the Capital Asset-pricing Model (CAPM) of Sharpe (1964), Lintner (1965), and Black (1972) and Ross's (1976) Arbitrage Pricing Theory (APT). Numerous attempts to explore the validity of these theories of modern finance have led to the identification of various firm specific …

    cape-town Repository record for Style anomalies on the Toronto Stock Exchange : a univariate, multivariate, style timing and portfolio sorting analysis (opens in a new tab)

  15. Efficient IC statistical modeling and extraction using a Bayesian inference framework

    Variability modeling and extraction in advanced process technologies is a key challenge to ensure robust circuit performance as well as high manufacturing yield. In this thesis, we present an ecient framework for device and circuit variability modeling and extraction by combining an ultra-compact …

    mit Repository record for Efficient IC statistical modeling and extraction using a Bayesian inference framework (opens in a new tab)

  16. Utility Accrual Real-Time Scheduling and Synchronization on Single and Multiprocessors: Models, Algorithms, and Tradeoffs

    … We consider the time/utility function (or TUF) timing model for specifying application time constraints, and the utility accrual (or UA) timeliness optimality criteria of satisfying lower bounds on accrued activity utility, and maximizing the total accrued utility. Efficient TUF/UA scheduling …

    vt Repository record for Utility Accrual Real-Time Scheduling and Synchronization on Single and Multiprocessors: Models, Algorithms, and Tradeoffs (opens in a new tab)

  17. Minimum-error, energy-constrained source coding by sensory neurons

    … coding is still not fully understood. Efforts to model neural coding could improve both the understanding of the nervous system and the design of artificial devices which interact with neurons. Sensory receptors and neurons transduce physical signals into a sequence of action potentials, called a …

    uiuc Repository record for Minimum-error, energy-constrained source coding by sensory neurons (opens in a new tab)