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Showing 1 to 12 of 12 for “"Through-Silicon-Vias (TSVs)"”.
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Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect
… that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in …
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Ferrite characterization techniques & particle simulations for semiconductor devices
… materials. The updated method is verified through full-wave simulations. In the second paper, a planar printed circuit board (PCB) coil is proposed as an alternative to the Keysight 16454A fixture for extracting permeability from ferrite materials. The method of extraction is verified …
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Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry
… that vertically stacks multiple layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered TSV profile can help to overcome the technical difficulties. However, an easily overlooked issue is that tapered TSV can cause wafer …
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Mechanism of SPS acceleration in a PEG containing copper plating bath
<p>Deposition of copper in Through Silicon Vias (TSVs) is achieved by addition of organic compounds, which act as suppressors and accelerants to copper electroplating solutions. The focus of this study is on the acceleration effect of bis-(3-sodiumsulfopropyl) disulfide (SPS) which is believed to …
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Predictive transient circuit simulations of charged device model ESD events in system in package chips
… die and 3D integrated circuits (3DICs) that use through-silicon vias (TSVs), and (c) estimate the peak CDM discharge current for any integrated circuit component with minimal knowledge of on-die circuits. Both the simulations and measurement results are presented in this document. The simulation …
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In-situ electrochemical spectroscopy and probe microscopy studies of electrodeposition
… levelers proposed for electroplating Cu in through-silicon vias (TSVs). The first study investigates the mechanism and morphology of chromate deposition, a process of which has significant importance both industrially and environmentally. Electrodeposition of chromate on Au was studied using …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
… to NOCs, 3D integration technology using through-silicon-vias (TSVs) can also alleviate the problems caused by long global interconnects and it offers more innovative design choices compared to traditional 2D integrated circuits (ICs).</p><p>Regardless of the choice of interconnect fabric, …
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Characterization, optimization, and simulation in through silicon via (TSV) dry etch
Two approaches of through-silicon-via (TSV) etching methods, the Bosch process (alternating etching/passivation phases) and the single-step etching, have been experimentally investigated and theoretically modeled in this study. Parameter ramping and post-etch plasma treatment techniques have been …
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Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts
… integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D …
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Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits
… which integrates micro-channel heat sinks into silicon substrates of the chip and uses liquid flow to remove heat inside the chip, is an effective active cooling scheme for 3D-ICs. While the micro-fluidic cooling provides excellent cooling to 3D-ICs, the associated overhead (cooling power …
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Performance variations due to layout-dependent stress in VLSI circuits
… optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor …
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
… applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects …