Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 21 for “"Through silicon vias"”.
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Effects of underfill material on solder deformation and damage in 3D packages
… The model solder joint is placed between two silicon substrates in contact with through-silicon vias without any other devices or components attached. Differing solder joint thicknesses, both with and without underfill, will be examined to study the effect on the stress and strain fields as …
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Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect
… that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in …
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Multilayer Micromachined RF MEMS Filters at Ka and L/S Band For On-Board Satellite Communication Systems
… (Ag) as an intermediate layer and fabrication of Through Silicon Vias (TSV).
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PI AND EMI ANALYSIS OF 3D IC SYSTEM WITH TSVS AND CO-PACKAGED OPTICS
… hysteresis behavior of a through-silicon-vias (TSV) structure in 3D IC and analyzing its effect on the power integrity of a system with 3D IC.</p> <p>This second paper investigates the scaled tendency of the emissions in a router system loaded with hundreds of optical …
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Numerical analysis of TSV/micro-bump deformation due to chip misalignment and thermal processing in 3D IC packages
… per volume and improved electrical performance through short vertical interconnect paths. Mechanical reliability of 3D IC packages is critical due to the widespread use of electronic devices. Misalignment induced shear deformation of the through-silicon vias (TSV) and solder micro-bumps are …
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Ferrite characterization techniques & particle simulations for semiconductor devices
… materials. The updated method is verified through full-wave simulations. In the second paper, a planar printed circuit board (PCB) coil is proposed as an alternative to the Keysight 16454A fixture for extracting permeability from ferrite materials. The method of extraction is verified …
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Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry
… that vertically stacks multiple layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered TSV profile can help to overcome the technical difficulties. However, an easily overlooked issue is that tapered TSV can cause wafer …
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Mechanism of SPS acceleration in a PEG containing copper plating bath
<p>Deposition of copper in Through Silicon Vias (TSVs) is achieved by addition of organic compounds, which act as suppressors and accelerants to copper electroplating solutions. The focus of this study is on the acceleration effect of bis-(3-sodiumsulfopropyl) disulfide (SPS) which is believed to …
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Characterization, optimization, and simulation in through silicon via (TSV) dry etch
Two approaches of through-silicon-via (TSV) etching methods, the Bosch process (alternating etching/passivation phases) and the single-step etching, have been experimentally investigated and theoretically modeled in this study. Parameter ramping and post-etch plasma treatment techniques have been …
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Predictive transient circuit simulations of charged device model ESD events in system in package chips
… die and 3D integrated circuits (3DICs) that use through-silicon vias (TSVs), and (c) estimate the peak CDM discharge current for any integrated circuit component with minimal knowledge of on-die circuits. Both the simulations and measurement results are presented in this document. The simulation …
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In-situ electrochemical spectroscopy and probe microscopy studies of electrodeposition
… levelers proposed for electroplating Cu in through-silicon vias (TSVs). The first study investigates the mechanism and morphology of chromate deposition, a process of which has significant importance both industrially and environmentally. Electrodeposition of chromate on Au was studied using …
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Analog-digital co-existence in 3D-IC
… is proposed. The inductor design utilizes the through-silicon-vias of the 3D stack as part of its geometry. The solenoid inductor exhibits a 28%larger inductance and a 6 dB higher quality factor compared to a conventional planar inductor occupying the same area. The VCO circuit phase noise is …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
… to NOCs, 3D integration technology using through-silicon-vias (TSVs) can also alleviate the problems caused by long global interconnects and it offers more innovative design choices compared to traditional 2D integrated circuits (ICs).</p><p>Regardless of the choice of interconnect fabric, …
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Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts
… integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D …
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Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits
… which integrates micro-channel heat sinks into silicon substrates of the chip and uses liquid flow to remove heat inside the chip, is an effective active cooling scheme for 3D-ICs. While the micro-fluidic cooling provides excellent cooling to 3D-ICs, the associated overhead (cooling power …
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Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs
… focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the …
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Using far-field measurements for determining mixed-mode interactions at interfaces
… the end loaded split (ELS) configuration for a silicon-epoxy interface, where the epoxy thickness was used to control the phase angle of the fracture mode-mix. Infra-red crack opening interferometry (IR-COI) was used to measure the normal crack opening displacements. For the resistance curves, …
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Refresh reduction in dynamic memories
… stacks. We propose the Xylem Thermal Through Silicon Via (TTSV) placement schemes, to reduce the temperature of the DRAM dies and the processor die in the stack. The TTSV placement should respect the DRAM array structure and handle unknown multicore hotspots. The resulting temperature …
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Performance variations due to layout-dependent stress in VLSI circuits
… optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor …
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