Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 14 of 14 for “"Through silicon via"”.
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A study of through-silicon-via (TSV) induced transistor variation
… difficult, 3D integration has emerged as a viable solution to achieve higher bandwidth and power efficiency. Through-siliconvias (TSVs), which directly connect stacked structures die-to-die, is one of the key techniques enabling 3D integration. The process steps and physical presence of …
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Characterization, optimization, and simulation in through silicon via (TSV) dry etch
Two approaches of through-silicon-via (TSV) etching methods, the Bosch process (alternating etching/passivation phases) and the single-step etching, have been experimentally investigated and theoretically modeled in this study. Parameter ramping and post-etch plasma treatment techniques have been …
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Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts
… integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D …
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Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry
… that vertically stacks multiple layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered TSV profile can help to overcome the technical difficulties. However, an easily overlooked issue is that tapered TSV can cause wafer …
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Stability analysis for SRAM cells with TSV induced stress in 3D ICs
… helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces large thermal mismatch stress in 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via …
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3D modeling and integration of current and future interconnect technologies
… are within 10% of Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs …
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Multiphysics modeling and simulation for large-scale integrated circuits
… of the multiphysics simulation is demonstrated through its applications in a variety of important problems, including the static and dynamic IR-drop analyses of power distribution networks, the thermal-ware high-frequency characterization of through-silicon-via structures, the full-wave …
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Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs
… focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the …
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Performance variations due to layout-dependent stress in VLSI circuits
… optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor …
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Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures
… with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal …
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Refresh reduction in dynamic memories
… stacks. We propose the Xylem Thermal Through Silicon Via (TTSV) placement schemes, to reduce the temperature of the DRAM dies and the processor die in the stack. The TTSV placement should respect the DRAM array structure and handle unknown multicore hotspots. The resulting temperature …
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Ferrite characterization techniques & particle simulations for semiconductor devices
… materials. The updated method is verified through full-wave simulations. In the second paper, a planar printed circuit board (PCB) coil is proposed as an alternative to the Keysight 16454A fixture for extracting permeability from ferrite materials. The method of extraction is verified …
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Thermal designs, models and optimization for three-dimensional integrated circuits
… adding thermal fin geometry to existing thermal through- silicon via (TTSV). We analyze design requirements of thermal fin for single TTSV as well as TTSV cluster designs with the goal of maximizing heat dissipation while minimizing the interference with routing and area consumption. An …
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Interconnect design techniques for multicore and 3D Integrated circuits.
… larger core. These cores must communicate through an efficient onchip interconnection network, by ideas such as networks-on-chips (NoCs), and NoC design is vital to both performance and power. This thesis presents solutions to the challenges in on-chip interconnect, more specifically, the …