Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 19 of 19 for “"Thread Level Parallelism"”.
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Performance Evaluation of Blocking and Non-Blocking Concurrent Queues on GPUs
… is crucial to the performance of multi-threaded programs in shared-memory systems. The arbitrary execution of concurrent threads, however, can result in an incorrect behavior of these data structures. Graphics Processing Units (GPUs) have appeared as a powerful platform for …
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High Performance Applications for the Single-Chip Message-Passing Parallel Computer
… Indeed, the method of exploiting instruction-level parallelism (ILP) within applications is reaching a point of diminishing returns. One approach to the aforementioned challenges is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP is a unique, tiled …
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Guided Automatic Binary Parallelisation
… is called BEEP (Binary Emulator for Estimating Parallelism), an extension to GBR for binary instrumentation. BEEP is used to identify potential thread-level parallelism through static binary analysis and binary instrumentation. BEEP performs preliminary static analysis on binaries and encodes …
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High Performance Sequential Execution In Fine-Grain Multicore Processors Via Core Aggregation
… core count, which is ideal for exploiting thread-level parallelism (TLP). However, sequential-code performance is significantly degraded. Enabling core fusion on such substrates proves to be very effective in boosting performance, and only with relatively small hardware overhead.
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Architectural support for massively-concurrent parallel computing
… rates. We will show that reliance on Instruction-Level Parallelism (ILP) for performance drives processor state upwards. When this massive state is not distributed across multiple program counters, processors choke on their own expensive context switches, here reconceptualized to show their true …
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Balancing Performance, Area, and Power in an On-Chip Network
… from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the …
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Microarchitectural Level Power Analysis And Optimization In Single Chip Parallel Computers
… efficient performance gains from Instruction Level Parallelism (ILP) are reaching a limit. Single-Chip Parallel Computers are promising solutions to the DSM design challenges and the performance limitations of ILP. These systems are explicitly modular architectures that efficiently support …
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Development and evaluation of a simultaneous multithreading processor simulator
… to achieve greater amounts of instruction level parallelism (ILP) and thread level parallelism (TLP). Simultaneous multithreading (SMT) is an architecture that exploits both LLP and TLP. It improves the utilization of the processor resources by allowing multiple independent threads to …
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The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer
… These features tend to exploit instruction level parallelism. However, a point of diminishing returns has been reached in this effort. Instead, these additional transistors could be used to take advantage of thread level parallelism (TLP). This type of parallelism focuses on hundreds of …
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Personalized Computer Architecture as Contextual Partitioning for Speech Recognition
… of processing elements per chip, yet no known parallelism form scales to that degree. To address this problem, we investigate the foundation of a computer architecture where processing elements and memory are contextually partitioned based upon facets of a user's life. Such Contextual …
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Implementation of a Hardware-Optimized MPI Library for the SCMP Multiprocessor
… The system is designed to take advantage of thread-level parallelism and to keep wire traces short in preparation for even smaller integrated circuit feature sizes. This thesis presents the implementation of the MPI (Message-Passing Interface) communications library on top of SCMP's hardware …
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Accelerated Adjoint Algorithmic Differentiation with Applications in Finance
… The application achieves favourable levels of parallelism on all three dimensions implemented by the GPU: Instruction Level Parallelism (ILP), Thread level parallelism (TLP), and Single Instruction Multiple Data (SIMD). We estimate the forward pass of the Milstein discretisation …
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Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology
… complexities and development needs, the modeling levels at which designers are working have quickly changed, as development at higher levels of abstraction allows for faster simulations of system models and earlier estimates of system performance while considering design trade-offs. Recent design …
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Evaluating the Scalability of SDF Single-chip Multiprocessor Architecture Using Automatically Parallelizing Code
… rate. A program exhibits different types of parallelism: instruction level parallelism (ILP), thread level parallelism (TLP), or data level parallelism (DLP). Likewise, architectures can be designed to exploit one or more of these types of parallelism. It is generally not possible to design …
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Malleable Contextual Partitioning and Computational Dreaming
… as decades-long, steady advances in instruction, thread level parallelism are coming to an end. And yet, conventional methods of parallelism fail to scale beyond 4-5 PE's, well short of the levels of parallelism found in the human brain. The human brain is able to maintain constant real time …
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Modeling and evaluation of multi-core multithreading processor architectures in SystemC
… techniques such as exploiting instruction-level parallelism have caused designers to shift their focus. Rather then focusing on single-threaded architectures, designers have increasingly sought to improve system performance and increase overall throughput by exploiting thread-level …
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On the Programmability and Performance of OpenCL Designs for FPGA
… has been the programming model, which uses a low-level hardware description language (HDL). Using HDLs require a detailed understanding of logic design and significant effort to implement and verify the behavioral models, with the latter growing with its complexity. Recent advancements in …
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Vector support for multicore processors with major emphasis on configurable multiprocessors
… forbade the exploration of more instruction-level parallelism (JLP). To continue raising the performance, processor designers then focused on thread-level parallelism (TLP) to realize a new architecture design paradigm. Multicore processor design is the result of this trend. It has proven …
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Improving the Off-chip Bandwidth Utilization and Energy Efficiency in Chip Multiprocessor (CMP) Architectures
… the early write-back technique for a two-level cache hierarchy in a CMP with four processor cores. Early write-back can be viewed as a modified cache write policy that takes into account not only maintaining data consistency between on-chip and off-chip components of the memory hierarchy …