Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 5 of 5 for “"Test architecture"”.
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High level behavioural modelling of boundary scan architecture.
… of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major …
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
… to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, …
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Design for pre-bond testability in 3D integrated circuits
… that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is …
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Value network modeling : a quantitative method for comparing benefit across exploration architectures
… be difficult to prioritize objectives for the architecture. I postulate that it is possible to make architectural decisions based on consideration of stakeholder value delivery, in order to help prioritize objectives. I introduce the concept of value network models to map out the indirect …
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Contribución a la gestión de los procesos de pruebas de software y servicios
… only provide a high level description of the testing phase. Because of that, test management activities fall under the general control of the project management process. However in a scenario where development project is carried out distributed big development teams, under different …