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Showing 1 to 3 of 3 for “"Test Application Time Reduction"”.
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Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Embargo set by: Seth Robbins for item 83238 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs
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Design for Testability Techniques to Optimize VLSI Test Cost
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test …
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Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems
… first we analyze and evaluate, the already known test data compression schemes for post-manufacturing testing and the DFT mechanisms for the enhancement of in-field testing and circuit reliability. We propose a new dictionary based test data compression method for post-manufacturing testing and we …