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Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 28 for “"TSV"”.
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A study of through-silicon-via (TSV) induced transistor variation
… and power efficiency. Through-siliconvias (TSVs), which directly connect stacked structures die-to-die, is one of the key techniques enabling 3D integration. The process steps and physical presence of TSVs, however, may generate a stress-induced thermal mismatch between TSVs and the silicon …
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Characterization, optimization, and simulation in through silicon via (TSV) dry etch
Two approaches of through-silicon-via (TSV) etching methods, the Bosch process (alternating etching/passivation phases) and the single-step etching, have been experimentally investigated and theoretically modeled in this study. Parameter ramping and post-etch plasma treatment techniques have been …
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Stability analysis for SRAM cells with TSV induced stress in 3D ICs
… 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. TSV-induced stress effects on electron/hole mobility and device performance will be studied for the widely used 6-transistor (6T) SRAM …
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Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts
… circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the …
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
… more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major …
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Numerical analysis of TSV/micro-bump deformation due to chip misalignment and thermal processing in 3D IC packages
… shear deformation of the through-silicon vias (TSV) and solder micro-bumps are simulated through an applied shearing action. Thermal effects due to coefficient of thermal expansion (CTE) mismatch during processing are also studied to provide trends of stress and deformation fields. Reliability …
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Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry
… layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered TSV profile can help to overcome the technical difficulties. However, an easily overlooked issue is that tapered TSV can cause wafer warpage during the fabrication processes. …
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3D modeling and integration of current and future interconnect technologies
… Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major …
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Role of virus genes in seed and aphid transmission and development of a virus-induced gene silencing system to study seed development in soybean
… mosaic virus (SMV) and Tobacco streak virus (TSV) are two important seed transmitted virus that infect soybean. SMV is a member of the family Potyviridae genus Potyvirus, and is transmitted by seed and aphids in soybean. The symptoms of SMV infection on soybean typically include mosaic and …
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Erste klinische Erfahrungen mit dem neuen Tracheostomaventil Window (Adeva)
… entscheidend durchsetzen. Das neu entwickelte TSV WindowÒ der Firma Adeva besitzt als einziges auf dem Markt eine Hustenklappe, alle anderen TSVe müssen zum Husten herausgenommen werden. Sowohl Sprech- als auch Hustenklappe sind individuell einstellbar und werden über Magnetkraft offen, bzw. …
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Towards low-power yet high-performance networks-on-chip
… a 3D-IC chip prototype of a throughsilicon via (TSV) interconnect that can support simultaneously bi-directional (SBD) signaling. While TSVs, as 3D-IC NoC links, offer an appealing solution to manycore architectures that require huge off-die bandwidth, existing TSV technologies impose …
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Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs
… the trade-offs between through silicon via (TSV) parasitics and heat sink performance. A TSV-compatible micropin-fin heat sink is designed, fabricated and thermally characterized in a single tier, and benchmarked with a conventional air-cooled heat sink. The designed heat sink has a thermal …
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Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures
… with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal …
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Multilayer Micromachined RF MEMS Filters at Ka and L/S Band For On-Board Satellite Communication Systems
… layer and fabrication of Through Silicon Vias (TSV).
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PI AND EMI ANALYSIS OF 3D IC SYSTEM WITH TSVS AND CO-PACKAGED OPTICS
… hysteresis behavior of a through-silicon-vias (TSV) structure in 3D IC and analyzing its effect on the power integrity of a system with 3D IC.</p> <p>This second paper investigates the scaled tendency of the emissions in a router system loaded with hundreds of optical modules, which can be …
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Molecular Characterization of Viruses Infecting Greenhouse Vegetables in Ontario
… mosaic virus (CGMMV), Tobacco streak virus (TSV), Pepper mild mottle virus (PMMoV), and Pepino mosaic virus (PepMV). The full-length genome sequences of BPEV, PMoV, and CGMMV have been cloned and sequenced. Since CGMMV causes the most severe economic lossess, we further characterized CGMMV …
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Performance variations due to layout-dependent stress in VLSI circuits
… are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor parameters that are seen even …
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Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits
… experimental purpose, small numbers (10-20) of TSVs, interconnects, bumps are fabricated together by hand calculation. However in the real 3D-IC design, thousands of TSVs, interconnects, bumps are reuired. Therefore, an automated CAD solution is required to provide precise physical design and …
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Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits
… resource conflict with through-silicon-vias TSVs or other structures). In this work, we investigate optimized micro-channel configurations that address the aforementioned considerations. We develop three micro-channel structures (hotspot optimized cooling configuration, bended micro-channel …
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An Investigation into the Effect of Gender and Clothing on Thermal Comfort and Energy Savings in Classrooms: A Case Study of University Buildings in the State of Kuwait
… mean vote (PMV) and thermal sensation vote (TSV) were examined in prior empirical investigations of thermal comfort in tropical settings. What is not fully understood, for example, is the impact of gender and clothing style (traditional/Islamic vs. western) on thermal comfort. As a result, …
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