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High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms

Agiakatsikas, DimitriosUNSW, Sydney2019

… is a high-level synthesis (HLS) tool, namely TLegUp, developed within the LegUp HLS framework. TLegUp triplicates Xilinx 7-series FPGA circuits during HLS rather than during the register-transfer level pre- or post-synthesis flow stage, as existing computer-aided design tools do. Results show …

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