Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 48 for “"System-on-chip (SoC)"”.
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Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools
"This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better …
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Improving Mobile SOC's Performance as an Energy Efficient DSP Platform with Heterogeneous Computing
Mobile system-on-chip (SOC) technology is improving at a staggering rate spurred primarily by the adoption of smartphones and tablets. This rapid innovation has allowed the mobile SOC to be considered in everything from high performance computing to embedded applications. In this work, modern SOC's …
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A low cost asynchronous eye diagram reconstruction system for high speed links
As link communication data rate increases, there is an increasing need for a more cost eective way to test and monitor signal integrity in link communication systems. Specifically, eye diagrams are valuable visual aids to analyze and quantify digital signal quality. This thesis presents a novel low …
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Design and Implementation of a Wearable Device for Prosopagnosia Rehabilitation
This study introduces a wearable facial recognition system for face blindness, or prosopagnosia, rehabilitation. Prosopagnosia is the inability to recognize familiar faces, which affects 2.5% of the world population (148 million people). The design and implementation of a facial recognition system …
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Kronos : verifying leak-free reset for a system-on-chip with multiple clock domains
Notary [3] uses formal verification to prove a hardware-level security property called deterministic start for a simple system-on-chip (SoC). Deterministic start requires that an SoC's state is fully reset by boot code to ensure that secrets cannot leak across reset boundaries. However, Notary's …
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Through-substrate interconnects for 3-D integration and RF systems
Interconnects on silicon chips are fabricated on the top surface with an ever-increasing number of metal layers necessary to just meet performance needs. While devices have scaled according to Moore's law, interconnects have lagged. As metal line widths shrink and line lengths increase, parasitic …
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Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B
Modern System-on-chip (SoC) hardware design puts considerable pressure on existing design and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for …
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FPGA Prototyping Framework on ARROW SoCKit Board with Xillybus Interface and Standard FIFO
… been a popular candidate in hardware acceleration for offloading compute-intensive tasks from the traditional microprocessors. Due to the parallel nature, algorithm functions implemented on FPGAs can provide acceleration and are more energy efficient than the software based counterparts on …
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Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation
… hardware quality. Specialized logic minimization tools have been built to make use of gate count as the primary optimization cost function. The first part of this thesis aims to investigate the effectiveness of such logical metrics in predicting hardware efficiency of corresponding circuits. …
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Cascaded Digital Refinement for Intrinsic Evolvable Hardware
Intrinsic evolution of reconfigurable hardware is sought to solve computational problems using the intrinsic processing behavior of System-on-Chip (SoC) platforms. SoC devices combine capabilities of analog and digital embedded components within a reconfigurable fabric under software control. A new …
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Polymorphic computing abstraction for heterogeneous architectures
<p>Integration of multiple computing paradigms onto system on chip (SoC) has pushed the boundaries of design space exploration for hardware architectures and computing system software stack. The heterogeneity of computing styles in SoC has created a new class of architectures referred to as …
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Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development
… adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces …
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HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet
Traditional static network addressing allows attackers the incredible advantage of taking time to plan and execute attacks against a network. To counter, Moving Target IPv6 Defense (MT6D) provides a network host obfuscation technique that dynamically obscures network and transport layer addresses. …
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HEMLOCK: HEterogeneous ModeL Of Computation Kernel for SystemC
As SystemC gains popularity as a System Level Design Language (SLDL) for System-On-Chip (SOC) designs, heterogeneous modelling and efficient simulation become increasingly important. The key in making an SLDL heterogeneous is the facility to express different Models Of Computation (MOC). Currently, …
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Implementation of a Neural Network-Based ASIC Chip for Mobile DNA Devices
… technology, has the potential to revolutionize genomics by making it accessible in a wide range of environments. However, current state-of-the-art devices face significant challenges due to the lack of integrated bioinformatics processing capabilities. This research addresses these …
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Efficient estimation and mitigation for radio-frequency interference
"With rapid innovations in Internet of Things (IoT) and wireless technology, more and more consumer electronic devices around the world are now connected to the internet. In a small form factor electronic device, there are plenty of potential noise sources such as System On Chip (SoC), high speed …
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Model based approach to Hardware/ Software Partitioning of SOC Designs
… industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of …
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Determination of correct operation and behaviour of a structured amorphous surface
A recurring theme in intelligent environments is the intelligent surface composed of nanoscale processing units (smart dust). Such a surface (iSurface) can be considered an amorphous computer composed of a large array of identical processing units (iCells) each with its own sensor/effectors. An …
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Drifting-dipole noise model of nanometer MOSFETs for radio frequency integrated circuit design
… opened a new era of high performance, low cost system-on-chip (SOC) designs for multi-gigabit-per-second wireless communication. However, such achievements also bring new challenges, particularly in modeling the physical behaviors of these super-scaled devices. Among these issues, it is found …
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Sound Synthesis Using Programmable System-On-Chip Devices
… name with digital technology, such as Novation and Arturia, have released analogue instruments. Although the feature set of digital synthesisers is extensive and with a falling comparative cost, the analogue market has continued to grow with more and more devices coming available. They are …
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