Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 119 for “"System On Chip"”.
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Sound Synthesis Using Programmable System-On-Chip Devices
… name with digital technology, such as Novation and Arturia, have released analogue instruments. Although the feature set of digital synthesisers is extensive and with a falling comparative cost, the analogue market has continued to grow with more and more devices coming available. They are …
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Reconfigurable System-on-Chip Architecture for Neural Signal Processing
… the brain's behavior in terms of its neuronal activity is the fundamental purpose of Brain-Machine Interfaces (BMIs). Neuronal activity is often assumed to be encoded in the rate of neuronal action potential spikes. Successful performance of a BMI system is tied to the efficiency of its …
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Investigation into low power and reliable system-on-chip design
It is likely that the demand for multiprocessor system-on-chip (MPSoC) with low power consumption and high reliability in the presence of soft errors will continue to increase. However, low power and reliable MPSoC design is challenging due to conflicting trade-off between power minimisation and …
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System-on-chip-based radiation imaging system with pulse shape discrimination capability
Compact scintillator array-based radiation imaging systems, capable of source characterization and localization of radioactive materials for nuclear security, safeguards, and non-proliferation applications, remain an unexplored technology as several technological challenges have prevented their …
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Implementing a ground penetrating radar user interface in system-on-chip technology
… a fast and accurate method for target location compare to other geophysical sensing techniques. An existing ground penetrating radar system developed by Open Fuel (Pty) Ltd is used in the detection and avoidance of obstacles for a sub-surface horizontal directional drill mechanism. This …
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Extensible Real-Time Sensor and Test Interface for a System-on-Chip
… of a printed circuit board (PCB) that enables connecting external sensors and a host computer to a custom Application-Specific Integrated Circuit (ASIC). The ASIC, previously developed by the Low-Energy Autonomy and Navigation research group, is designed for autonomous navigation on microrobots, …
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Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design
This dissertation addresses two important problems in reusing intellectual properties (IPs) in the form of reusable design or verification components. The first problem is associated with fast and effective integration of reusable design components into a System-on-chip (SoC), so faster design …
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Entwurf, Methoden und Werkzeuge für komplexe Bildverarbeitungssysteme auf Rekonfigurierbaren System-on-Chip-Architekturen
Bildverarbeitungsanwendungen stellen besondere Ansprüche an das ausführende Rechensystem. Einerseits ist eine hohe Rechenleistung erforderlich. Andererseits ist eine hohe Flexibilität von Vorteil, da die Entwicklung tendentiell ein experimenteller und interaktiver Prozess ist. Für neue Anwendungen …
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Tecniche per il controllo dinamico del consumo di potenza per piattaforme system-on-chip
Providing support for multimedia applications on low-power mobile devices remains a significant research challenge. This is primarily due to two reasons: • Portable mobile devices have modest sizes and weights, and therefore inadequate resources, low CPU processing power, reduced display …
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HarmonySched: Dynamically scheduling multiple concurrent machine learning models across a heterogeneous system on chip
… use all the resources provided by such chips. Motivated by various AI applications, modern SoC systems integrate components such as GPUs and NPUs. Very few studies address scheduling multiple concurrent workloads and dynamically arriving workloads on these SoCs. This study introduces a …
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Kronos : verifying leak-free reset for a system-on-chip with multiple clock domains
Notary [3] uses formal verification to prove a hardware-level security property called deterministic start for a simple system-on-chip (SoC). Deterministic start requires that an SoC's state is fully reset by boot code to ensure that secrets cannot leak across reset boundaries. However, Notary's …
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Advanced MIMO-CDMA receiver for interference suppression: Algorithms, system-on-chip architectures and design methodology
… Multiple Output) technology is proposed in CDMA systems for much higher rate packet services. The receiver architecture is essential for the mobile devices to support high speed multimedia service. The design challenges come from both detection algorithms and hardware architectures. Much more …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
<p>With the continuous scaling of transistors to smaller dimensions, it has now become feasible to pack billions of transistors in a single chip. However, interconnect does not scale as well as transistors; hence a significant amount of research is focused today on finding viable alternatives to …
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Low-power System-on-Chip Processors for Energy Efficient High Performance Computing: The Texas Instruments Keystone II
… Computing (HPC) community recognizes energy consumption as a major problem. Extensive research is underway to identify means to increase energy efficiency of HPC systems including consideration of alternative building blocks for future systems. This thesis considers one such system, the Texas …
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Low-power System-on-Chip Processors for Energy Efficient High Performance Computing: The Texas Instruments Keystone II
… Computing (HPC) community recognizes energy consumption as a major problem. Extensive research is underway to identify means to increase energy efficiency of HPC systems including consideration of alternative building blocks for future systems. This thesis considers one such system, the Texas …
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Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B
Modern System-on-chip (SoC) hardware design puts considerable pressure on existing design and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for …
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