Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Stuck-at fault"”.
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Topics in Totally Self-Checking Circuits and Testable Cmos Circuits
… purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives an error indication. It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing …
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Use of architectural-level primitives in system-level diagnosis and speed up of test vector generation
Test generation is an important part of a circuit as the test vectors are used during the design, manufacture, system integration, and throughout the life-cycle of the circuit in order to detect the presence of defects. The very large scale integration (VLSI) test generation problem has been one of …
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Micro-operation perturbations in chip level fault modeling
… approach, a difficult question to answer is: What is the best micro-operation perturbation for modeling fault at the chip level? In this thesis, an automatic evaluation system is developed to determine the best micro-operation perturbation. The measure used is the gate level stuck-at fault …
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On detection of stuck-open faults using stuck-at test sets in CMOS combinational circuits
The traditional line stuck-at fault model does not properly represent transistor stuck-open (SOP) faults in complementary metal oxide semiconductor (CMOS) circuits. In general, test generation methods for detecting CMOS SOP faults are complex and time consuming due to the sequential behavior of …
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Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test
With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate …
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Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
Fault collapsing, test generation, and fault simulation were traditionally developed at the gate-level based on the stuck-at fault model. However, with the advent of VLSI MOS technology, this fault model is not applicable. In order to reduce the number of faults which need to be considered in the …
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Robust and reliable hardware accelerator design through high-level synthesis
… resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide …