Global ETD Search
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Showing 1 to 17 of 17 for “"Static Timing Analysis"”.
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Parallel and heterogeneous computing for static timing analysis
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms
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Boosting static timing analysis with programming and algorithmic approaches
… demand for faster design closure. As a primary timing measurement tool frequently used in design stage and optimization stage, static timing analysis has become one of the major performance bottlenecks in digital design. We study a novel parallel programming model and algorithm to boost timing …
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Tutorial on direct digital synthesizer structure improvements and static timing analysis
The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have …
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Computationally efficient characterization of standard cells for statistical static timing analysis
… propose a computationally efficient statistical static timing analysis (SSTA) technique that addresses intra-die variations at near-threshold to sub-threshold supply voltage, simulated on a scaled 32nm CMOS standard cell library. This technique would characterize the propagation delay and output …
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Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests
… is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation.</p> <p>We first describe a deterministic …
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A PCI Express to PCIX Bridge optimized for performance and area
… system verification environment, synthesis, static timing analysis, and performance and area evaluations. The work has been completed in IBM Microelectronics in Burlington, Vermont as part of the MIT VI-A Program.
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Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications
… the process. Modeling of the memory arrays for static timing analysis (STA) is done to allow easy integration of the design into a typical RTL design flow. System simulation data is incorporated into block-level simulations to validate the memory timing models. Hardware testing over five …
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Hardware implementation of a low-power two-dimensional discrete cosine transform
… verification methods, synthesis operations, static timing analysis, design for test compliance, power analysis, and performance comparisons for the development of the core. The work has been completed in the ASIC Digital Cores I department of the IBM Microelectronics Division in Burlington, …
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Delay Analysis of Digital Circuits Using Prony's Method
… possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the …
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Two concrete problems in timing analysis of embedded software
Static timing analysis is crucial for the design of real-time embedded systems. Static analysis methods analyze a program statically to give an upper bound on the worst case execution time (WCET) of the program. The problem of determining WCET of a program by static analysis methods has to be …
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Timing Analysis and Behavioral Synthesis with Process Variation
… with process variation is the need for accurate timing analysis in which process parameters such as gate length and oxide thickness are now modeled as probability density functions (pdf) instead of deterministic quantities. Statistical static timing analysis (SSTA) has emerged to fi ll that void. …
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Gate-level timing analysis and waveform evaluation
<p>Static timing analysis (STA) is an integral part of modern VLSI chip design. Table lookup based methods are widely used in current industry due to its fast runtime and mature algorithms. Conventional STA algorithms based on table-lookup methods are developed under many assumptions in timing …
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High-Level Resource Binding and Allocation for Power and Performance Optimization
… the design hierarchy through its inclusion of a timing-driven floorplanner guided by a statistical static timing analysis engine which is used to modify and enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are …
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Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits
Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-04-21T15:49:15Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Rogachev_Artem.docx: 719809 bytes, checksum: a5e99a79e062ca8794a0646df6052ac8 (MD5) Rogachev_Artem.pdf: 1216501 bytes, …
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Architecture and CAD for nanoscale and 3d FPGA
… physical design tools are used, with statistical static timing analysis (SSTA) that can handle both Gaussian and non-Gaussian random variables. A 2.75× performance improvement is seen over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5× footprint reduction compared to a …
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Performance variations due to layout-dependent stress in VLSI circuits
… of layout dependent stress during circuit analysis. Evaluating circuit performance involves modeling the stress distributions in the layout accurately and translating the mechanical abstraction of the layout to circuit-level abstraction. This thesis develops scalable techniques to …
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Architecture and CAD for carbon nanomaterial integrated circuits
… physical design tools are used, with statistical timing analysis that can handle both Gaussian and non-Gaussian random variables. When the FPCNA architecture is evaluated using this CAD flow, a 2.75× performance improvement is seen over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA …