Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 13 of 13 for “"Static Power Consumption"”.
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Predictive comparators with adaptive control
… to null the error. Emphasis is placed on low power consumption, including the development of a linear predictor with no static power consumption. Improvements of two orders of magnitude in power-delay product are demonstrated. The adaptive comparator is ideally suited for applications such as …
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An Application Framework for a Power-Aware Processor Architecture
… based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.
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Design of a Power-aware Dataflow Processor Architecture
… domains. Therefore, this thesis presents a power-aware dataflow processor architecture targeted for the electronic textile computing space. The processor architecture has no instructions, and handles multiple events inherently without deploying software methods. This thesis also shows that …
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Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
… use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the …
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Evaluation and Analysis of NULL Convention Logic Circuits
… increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness. </p> <p>While NULL Convention Logic (NCL) has been implemented in a variety of applications, …
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Equalized on-chip interconnect : modeling, analysis, and design
… techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a fast-design space exploration methodology is …
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Superconducting Nanowire Integrated Circuits for Scalable Cryogenic Memory
… nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable …
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Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating
… energy, using up battery life. Increasing power consumption is a rising concern to users and researchers alike. Power gating, turning off a blocks of hardware when idle, reduces static power consumption. The Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) currently employed in …
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Imperfection-Aware Design of CNFET Digital VLSI Circuits
… that cause performance variation, large static power consumption, and yield degradation. We present an imperfection-aware design technique for CNFET digital VLSI circuits by: 1) Analytical models that are developed to analyze and quantify the effects of CNT density variation on device …
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Shape formation by self-disassembly in programmable matter systems
… enable the modules to communicate and share power with their nearest neighbors. These solid-state connectors are strong enough for a single inter-module connection to support the weight of 80 other modules. The connectors only consume power when switching on or off; they have no static power …
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Metal oxide thin film transistors for CMOS applications
… transistors (TFTs) is essential to reduce the power consumption and increase the complexity of low-cost (flexible) processors. These processors have the potential to create ultralow-cost (~1 pence) chips that can turn everyday objects into smart-objects. This thesis presents research on the …
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Silicon-Based RFIC Multi-band Transmitter Front Ends for Ultra-Wideband Communications and Sensor Applications
… unique features such as broad bandwidth, low power, accurate position location capabilities, etc. This research focuses on the RFIC front-end hardware design issues for proposed UWB transmitters. Two different methods of multiband frequency generation ----- using switched capacitor VCO tanks …
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Energy-efficient data converter design in scaled CMOS technology
… converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator …