Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 12 of 12 for “"Standard cell library"”.
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ALA ASIC : a standard cell library for Asynchronous Logic Automata
This thesis demonstrates a hardware library with related tools and designs for Asynchronous Logic Automata (ALA) gates in a generic 90nm process development kit that allows a direct one-to-one mapping from software to hardware. Included are basic design tools to enable writing ALA software, the …
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Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development
Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers …
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Analysis of MOS Current Mode Logic (MCML) and Implementation of MCML Standard Cell Library for Low-Noise Digital Circuit Design
… when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high …
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Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization
… all parameters vary together during fabrication. Standard cell library design and characterisation is also explained, which is essential to perform simulations on large circuits that HSPICE is unable to handle. The standard cell library is also constructed and tested on four circuits to validate …
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Algorithms and Architectures for Soft -Decoding Reed -Solomon Codes
… is synthesized using the Virtual Silicon standard cell library in a 0.13-mum CMOS process. It has an area of 7.29 mm² and achieves a throughput of 8 Gbps.
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Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool
… based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a …
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Design of low-power digital circuits in the sub-threshold domain
… problem. Our work consists of three parts; 1) a standard cell library optimized for subthreshold operation, 2) couple of level shifter circuits capable of sub-threshold to above threshold voltage conversion and 3) a subthreshold memory array. We have used the 28nm FD-SOI technology from ST …
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Computationally efficient characterization of standard cells for statistical static timing analysis
… supply voltage, simulated on a scaled 32nm CMOS standard cell library. This technique would characterize the propagation delay and output slew of an individual cell for subsequent timing path analyses. Its efficiency stems from the fact that it only needs to find the delay or output slew in the …
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VLSI Physical Design for Manufacturability and Reliability
… boundary based method are proposed to enable the cell-wise optical proximity correction (OPC) for 32nm node and beyond. It will saves weeks of computation on full-chip OPC and reduce the exponentially increase mask data volume. Our proposed methodology will also lead to more accurate timing model …
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Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization
… takes the features of modern timing models from standard cell library. With our new timing model, we are able to formulate the combinatorial discrete sizing problem as a simplified mathematical expression and apply it to existing Lagrangian relaxation method, which is shown to converge to optimal …
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Design Automation and Evaluation Of Emerging 3D – IC Technology Using Stacked Horizontal Nanowires
… and evaluate the SN3D circuits from fundamental cell level (standard cell level) to system level using industry standard EDA tools from Cadence Design Systems. A standard cell library containing three cells is designed and benchmarked with 2D CMOS. A system level flow is implemented for a …
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Optimization for advanced lithography
… gate must abut at least one source node after standard cell placement. If the drain nodes at two adjacent cell boundaries abut each other, additional source nodes must be inserted in between for dummy gate power tying, which takes more placement area. We propose a detailed placement …