Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 63 for “"Standard Cell"”.
-
Parallel algorithms for standard cell placement using simulated annealing
… been the most popular and effective methods for cell placement. In this thesis, parallelization approaches to simulated-annealing-based standard cell placement are presented.
-
ALA ASIC : a standard cell library for Asynchronous Logic Automata
… favorite high level language and run it on a standard processor. However, the widening gap between traditional models of computation and the reality of the underlying hardware has led to massive costs for design and fabrication as well as numerous issues for scalability and portability. Unlike …
-
Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development
Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers …
-
Analysis of MOS Current Mode Logic (MCML) and Implementation of MCML Standard Cell Library for Low-Noise Digital Circuit Design
… when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high …
-
Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization
… all parameters vary together during fabrication. Standard cell library design and characterisation is also explained, which is essential to perform simulations on large circuits that HSPICE is unable to handle. The standard cell library is also constructed and tested on four circuits to validate …
-
On the Characterization of Library Cells
… method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of …
-
Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool
… based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a …
-
Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities
In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing variations can be characterized by the timing model. However, as regular design rules become necessary in sub-45 nm node circuit …
-
An Expert System for VLSI Layout
… methodology that eliminates the weakness of a standard cell layout system. Our methodology decomposes the module layout problem into a smaller leaf-cell layout problem and designs the leaf-cells exactly according to their environmental needs.
-
Parallel algorithms for placement and routing in VLSI design
… algorithms for two VLSl synthesis tasks, standard cell placement and global routing.
-
Combinatorial optimization by stochastic evolution with applications to the physical design of VLSI circuits
… Circuit, Traveling Salesman, Linear Ordering, Standard Cell Placement, and Multi-way Circuit Partitioning problems. It is empirically shown that SE out-performs the more established general optimization algorithm, namely, Simulated Annealing.
-
Timing-driven optimization problems in VLSI CAD
… Programmable Gate Arrays (FPGAs), identical standard cell based architectures and WSI arrays of blocks having a regular structure are the major architectures that are regular. The regularity of these architectures allows us to use powerful graph theoretic techniques that would not be possible …
-
Physiological Oxygen and Media Conditions Influence Breast Cancer Hallmarks in Vitro
Standard cell culture conditions often fail to replicate the in vivo microenvironment, limiting the reproducibility and physiological relevance of experimental findings. For example, commonly used media such as Dulbecco’s Modified Eagle Medium (DMEM) contain supraphysiological levels of key …
-
Analysis of the roles of ligand and DNA binding in estrogen receptor action
… work we provide evidence indicating that under standard cell culture conditions unliganded estrogen receptor (ER) is unable to activate transcription. Studies of Chinese Hamster Ovary cells which were grown under serum-free conditions, suggested that commercial base media may contain traces of …
-
Analysis and design of power electronic cell for modular power electronic systems: DC-AC converter configurations
… requirement of high degree of integration and standardization of modern electrical power supply systems, the easy to use power processing configuration is becoming increasingly important. The main objective of the present research is to develop a standard cell and to meet the requirement of …
-
Design Automation and Evaluation Of Emerging 3D – IC Technology Using Stacked Horizontal Nanowires
… and evaluate the SN3D circuits from fundamental cell level (standard cell level) to system level using industry standard EDA tools from Cadence Design Systems. A standard cell library containing three cells is designed and benchmarked with 2D CMOS. A system level flow is implemented for a …
-
On a Viterbi decoder design for low power dissipation
… proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of Viterbi decoders for wireless communications applications. In CMOS …
-
Algorithms and Architectures for Soft -Decoding Reed -Solomon Codes
… is synthesized using the Virtual Silicon standard cell library in a 0.13-mum CMOS process. It has an area of 7.29 mm² and achieves a throughput of 8 Gbps.
-
Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling
… external latchup. The latchup susceptibility of standard cell based designs is also investigated. Guard rings are used to reduce latchup susceptibility and to reduce the substrate noise coupled to sensitive analog circuits. In this work, the effectiveness of different guard ring topologies for …
-
Optimization for advanced lithography
… gate must abut at least one source node after standard cell placement. If the drain nodes at two adjacent cell boundaries abut each other, additional source nodes must be inserted in between for dummy gate power tying, which takes more placement area. We propose a detailed placement …
Page 1 of 4