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Showing 1 to 2 of 2 for “"Stacked DRAM"”.
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Architectural techniques to extend multi-core performance scaling
… memory bandwidth problem. Die-stacking of DRAM on a processor die promises to continue scaling the pin bandwidth to off-chip memory. While the die-stacked DRAM is expected to be used as a cache, storing any part of the tag in the DRAM itself erodes the bandwidth advantage of die-stacking. …
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Intelligent cache management for heterogeneous memory systems
DRAM caches are important for enabling effective heterogeneous memory systems that can transparently provide the bandwidth of high-bandwidth memories and the capacity of high-capacity memories. This dissertation investigates enabling intelligent cache management for tag-inside-cacheline DRAM cache …