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Showing 1 to 20 of 35 for “"Speculative execution"”.

  1. Controlling speculative execution through a virtually ordered memory system

    Processors which extract parallelism through speculative execution must be able to identify when mis-speculation has occurred. The three places where mis-speculation can occur are register accesses, control flow prediction and memory accesses. Controlling register and control flow speculation has …

    waikato-masters Repository record for Controlling speculative execution through a virtually ordered memory system (opens in a new tab)

  2. Cabala : a speculative execution framework to make Linux services fault tolerant

    Cabala is a speculative execution framework that enables server programs in Linux to be fault tolerant. The errors it targets are run-time errors that are due to program bugs, and which cause program exit; in particular, it provides resilience to errors triggered by requests. The Cabala framework …

    mit Repository record for Cabala : a speculative execution framework to make Linux services fault tolerant (opens in a new tab)

  3. Improving performance and security of indirect memory references on speculative execution machines

    … memory references hobble efficient and secure execution on current processor architectures. Traditional hardware techniques such as caches and speculative execution are ineffective on demanding workloads, such as in-memory databases, machine learning, and graph analytics. While terabytes of …

    mit Repository record for Improving performance and security of indirect memory references on speculative execution machines (opens in a new tab)

  4. Exploiting Instruction Level Parallelism in the Presence of Conditional Branches

    For many applications, speculative execution alone is not sufficient to achieve high performance. The fundamental limitation is that speculation only removes dependences between branches and other instructions. The branches themselves remain in the code, which causes difficult problems. This …

    uiuc Repository record for Exploiting Instruction Level Parallelism in the Presence of Conditional Branches (opens in a new tab)

  5. Pensieve: Microarchitectural Modeling for Security Evaluation

    … energy of a processor design. With the advent of speculative execution attacks and their security concerns, these traditional modeling techniques fall short when used for security evaluation of defenses against these attacks. This thesis presents Pensieve, a security evaluation framework targeting …

    mit Repository record for Pensieve: Microarchitectural Modeling for Security Evaluation (opens in a new tab)

  6. Scalable and Broad Hardware Acceleration through Practical Speculative Parallelism

    … to build accelerators for applications with speculative parallelism. These applications consist of atomic tasks, sometimes with order constraints, and need speculative execution to extract parallelism. In speculative execution, tasks are executed in parallel assuming they are independent. A …

    mit Repository record for Scalable and Broad Hardware Acceleration through Practical Speculative Parallelism (opens in a new tab)

  7. SUDS : automatic parallelization for raw processors

    … queue conversion compiler transformation is speculative, in the sense that it may introduce dynamic memory allocation operations into code that would not otherwise dynamically allocate memory. Thus, SUDS also includes a transactional runtime system that periodically checkpoints machine state, …

    mit Repository record for SUDS : automatic parallelization for raw processors (opens in a new tab)

  8. Analysis and Enforcement of Properties in Software Systems

    … of the underlying processor, such as cache and speculative execution, which may undermine their soundness guarantees. To fill the gap, I propose a set of new methods and tools for ensuring the safety and security of software systems. Broadly speaking, these methods and tools fall into three …

    vt Repository record for Analysis and Enforcement of Properties in Software Systems (opens in a new tab)

  9. Task Scheduling Techniques to Accelerate RTL Simulation

    … key opportunities. First, it performs dataflow execution of small tasks to leverage the fine-grained parallelism in simulation workloads. Dataflow execution exposes abundant parallelism, as each task can run as soon as its inputs are available. Second, it performs selective event-driven …

    mit Repository record for Task Scheduling Techniques to Accelerate RTL Simulation (opens in a new tab)

  10. Type Checker for Annotated Assembly Programs

    The rise of speculative-execution attacks, such as Spectre, has presented a security challenge to developers. Speculation on secret data can expose it, but running without speculation is suboptimal for runtime. To fix this, researchers have been evaluating “smart” speculation schemes, which …

    mit Repository record for Type Checker for Annotated Assembly Programs (opens in a new tab)

  11. Compiler-assisted debugging and multiple instruction retry

    Backward execution requires the saving of historic information concurrently with the normal execution in order for a program to roll back. There are several applications for which backward execution is useful. In an environment where reliability is a concern, it may be necessary to roll back the …

    uiuc Repository record for Compiler-assisted debugging and multiple instruction retry (opens in a new tab)

  12. Multiple-Pass Pipelining: Enhancing in-Order Microarchitectures to Out-of-Order Performance

    … allowing overlapping of useful ""advanced"" execution with miss resolution. Multipass pipelining is based upon a similar concept, but overcomes the shortfalls of two-pass pipelining through simultaneous execution of architectural and advance instructions on a common pipeline in a simultaneous …

    uiuc Repository record for Multiple-Pass Pipelining: Enhancing in-Order Microarchitectures to Out-of-Order Performance (opens in a new tab)

  13. BlueVeri: Formal Security Verification for Bluespec Processor Designs

    … the security of a Bluespec processor against speculative execution attacks. BlueVeri leverages the high-level information provided by Bluespec’s guarded atomic actions, simplifying and accelerating the verification process. We evaluate BlueVeri on out-of-order processors implemented in …

    mit Repository record for BlueVeri: Formal Security Verification for Bluespec Processor Designs (opens in a new tab)

  14. Toward transient-execution attack mitigations on CHERI

    … RISC Instructions (CHERI) systems from transient-execution attacks. Transient-execution attacks shocked the computing world as they allow security mechanisms to be circumvented via seemingly safe performance-enhancing mechanisms. These attacks use misguided speculation to access secrets and …

    cambridge Repository record for Toward transient-execution attack mitigations on CHERI (opens in a new tab)

  15. Performant and Resilient Service Composition for Modern Cloud Applications

    … distributed protocol that allow optimistic, speculative execution ahead of slower fault-tolerance safeguards. Together, these pieces allow developers to assemble fault-tolerant distributed systems that are correct by construction and often more performant than existing solutions.

    mit Repository record for Performant and Resilient Service Composition for Modern Cloud Applications (opens in a new tab)

  16. Leveraging concurrency for performance and security

    … flow across the Last Level Cache or across the speculative execution boundary. Covert channels encode secret values in sub-architectural features like caches and buffers. To detect covert channels we propose techniques similar to our RnR-Safe approach. First, the original instruction execution

    uiuc Repository record for Leveraging concurrency for performance and security (opens in a new tab)

  17. Architectural support for commutativity in hardware speculation

    Hardware speculative execution schemes (e.g., hardware transactional memory (HTM)) enjoy low run-time overheads but suffer from limited concurrency because they detect conflicts at the level of reads and writes. By contrast, software speculation schemes can reduce conflicts by exploiting that many …

    mit Repository record for Architectural support for commutativity in hardware speculation (opens in a new tab)

  18. Brute-force resistant Pointer-Authentication using RISC-V co-processor

    … to brute-force attacks, particularly under speculative execution vulnerabilities such as PACMAN [2]. To overcome these limitations, this thesis proposes a pointer encryption scheme wherein the full 64-bit pointer is encrypted using low-latency block ciphers like PRINCEv2 [3]. This design has …

    vt Repository record for Brute-force resistant Pointer-Authentication using RISC-V co-processor (opens in a new tab)

  19. Hardening Trusted Execution Environments Against Microarchitectural Side-Channel Attacks: A Constructive Approach

    Trusted Execution Environments (TEEs) [1–5] promised to enable secure computation even in the presence of privileged adversaries by providing hardware-enforced isolation. However, the discovery of microarchitectural side-channel and transient execution attacks [6–10] has severely undermined these …

    mit Repository record for Hardening Trusted Execution Environments Against Microarchitectural Side-Channel Attacks: A Constructive Approach (opens in a new tab)

  20. Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution

    … key opportunities. First, it performs dataflow execution of small tasks to leverage the fine-grained parallelism in simulation workloads. Second, it performs selective event-driven execution to run only the fraction of the design exercised each cycle, skipping ineffectual tasks. ASH hardware …

    mit Repository record for Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution (opens in a new tab)

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