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Showing 1 to 1 of 1 for “"Solder Joint Reliability, Finite Element Analysis, 65nm Cu/low-k, Large die, Flip Chip Package"”.
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Structural Design and Optimization of 65nm Cu/low-k Flipchip Package
… design of Charteredb s C65 nm 21 mm x 21 mm die size FCBGA package incorporated with fully active and functional 9-metal Cu/ low-k layers and 150um interconnect pitch. The low-k material used in this study is non-porous SiCOH with a k value of 2.9. A parametric study using 2D plane strain …