Global ETD Search

Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.

Results

Showing 1 to 2 of 2 for “"Sleep Convention Logic"”.

  1. Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

    … are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. </p> <p>This dissertation investigates new areas in NCL design …

    arkansas Repository record for Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures (opens in a new tab)

  2. Comparison of Various Pipelined and Non-Pipelined SCl 8051 ALUs

    … ALU with two versions: SCL 8051 ALU with <em>nsleep</em> and <em>sleep</em> signals and SCL 8051 ALU without <em>nsleep</em>. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs …

    arkansas Repository record for Comparison of Various Pipelined and Non-Pipelined SCl 8051 ALUs (opens in a new tab)