Global ETD Search

Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.

Results

Showing 1 to 10 of 10 for “"Silent data corruption"”.

  1. FAST AND SECURE INTEGRITY VERIFICATION FOR HIGH-SPEED DATA TRANSFERS

    The amount of data generated by scientific and commercial applications is growing at an ever-increasing pace. This data is often moved between geographically distributed sites for various purposes such as collaboration and archival, leading to significant increase in data transfer rates. Surge in …

    unr Repository record for FAST AND SECURE INTEGRITY VERIFICATION FOR HIGH-SPEED DATA TRANSFERS (opens in a new tab)

  2. Probabilistic Approach to Avoid Uncorrectable Bit Errors in Storage Systems

    Silent data corruption in storage system poses a significant risk to the integrity ofdata. While error correction codes (ECC) can recover the majority of the errors, a non-negligible portion of them escape ECC, referred to as uncorrectable errors. As the scale of storage systems increases, the mean …

    unr Repository record for Probabilistic Approach to Avoid Uncorrectable Bit Errors in Storage Systems (opens in a new tab)

  3. Mitigation of failures in high performance computing via runtime techniques

    … supercomputers. The smaller the transistors are, silent data corruptions (SDC) are likely to occur more frequently. SDCs do not inhibit execution, but may silently lead to incorrect results. In this thesis, we leverage runtime system and compiler techniques to mitigate a significant fraction of …

    uiuc Repository record for Mitigation of failures in high performance computing via runtime techniques (opens in a new tab)

  4. POSEIDON: The First Safe and Scalable Persistent Memory Allocator

    … for an NVMM allocator to guarantee its heap metadata safety from both internal and external errors. An effective NVMM memory allocator should be 1) safe 2) scalable and 3) high performing. Unfortunately, none of the existing persistent memory allocators achieve all three requisites; critically, …

    vt Repository record for POSEIDON: The First Safe and Scalable Persistent Memory Allocator (opens in a new tab)

  5. From experiment to design – fault characterization and detection in parallel computer systems using computational accelerators

    … to demonstrate the importance of detecting silent data corruption (SDC) errors that are mainly due to the lack of fine-grained protections and the massive use of fault-insensitive data. This dissertation also presents transparent fault tolerance frameworks and techniques that are directly …

    uiuc Repository record for From experiment to design – fault characterization and detection in parallel computer systems using computational accelerators (opens in a new tab)

  6. Ensuring reliable and secure deployment of emergent workloads on modern microprocessors

    … reports from major cloud vendors describing new silent data corruption (SDC) behaviors at scale suggests a change in the nature of faults in the wild. Recent publications suggest that one root cause of these SDCs may be small delay faults (SDFs) induced by marginal defects. While …

    tu-berlin Repository record for Ensuring reliable and secure deployment of emergent workloads on modern microprocessors (opens in a new tab)

  7. From detection to optimization: impact of soft errors on high-performance computing applications

    … the types of errors facing HPC, soft errors that silently corrupt system or application state are among the most severe. The behavior of HPC applications in the presence of soft errors is critical to gain insight for effective utilization of HPC systems. The need to understand this behavior can be …

    uiuc Repository record for From detection to optimization: impact of soft errors on high-performance computing applications (opens in a new tab)

  8. New techniques for the Reliability Evaluation of AI-oriented Hardware Accelerators

    L'abstract è presente nell'allegato / the abstract is in the attachment

    poli-torino Repository record for New techniques for the Reliability Evaluation of AI-oriented Hardware Accelerators (opens in a new tab)

  9. Low-cost error detection through high-level synthesis

    … for circuit reliability is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling flexibility of high-level synthesis to detect control errors through diverse binding and minimize area cost …

    uiuc Repository record for Low-cost error detection through high-level synthesis (opens in a new tab)

  10. Robust and reliable hardware accelerator design through high-level synthesis

    … designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing …

    uiuc Repository record for Robust and reliable hardware accelerator design through high-level synthesis (opens in a new tab)