Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 16 of 16 for “"Shared memory system"”.
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A Shared Memory System for Fresh Breeze
The Shared Memory System (SMS) for Fresh Breeze, a multiprocessor chip guided by modular programming principles, provides a global space from which all the fresh breeze processors access chunks of memory. The SMS supports the operations of: obtaining unique identifiers for new chunks; storing a …
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DSM64: A Distributed Shared Memory System in User-Space
… a lazy release consistent software distributed shared memory (SDSM) system built entirely in user-space. The DSM64 system is capable of executing threaded applications implemented with pthreads on a cluster of networked machines without any modifications to the target application. The DSM64 …
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Protocol optimizations for the CRL distributed shared memory system
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 1996.
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A fault-tolerant shared memory system architecture for a Byzantine resilient computer
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.
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The design and performance analysis of an arbiter for a multi-processor shared-memory system
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1984.
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Speculative Shared -Memory Architectures
… and parallel codes. We propose a speculative shared-memory system to extract parallelism from codes for which today's parallelizing compilers fail. We distance ourselves from the existing literature by targeting scalability and modularity: Our hierarchical approach largely abstracts away the …
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Constructing and evaluating weak memory models
A memory model for an instruction set architecture (ISA) specifies all the legal multithreaded-program behaviors, and consequently constrains processor implementations. Weak memory models are a consequence of the desire of architects to preserve the flexibility of implementing optimizations that …
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Compiling array computations for the Fresh Breeze Parallel Processor
… determinate execution with a write-once shared memory system. In particular, Fresh Breeze data structures must be constructed from directed acyclic graphs of immutable fixed-size chunks of memory, rather than laid out in a mutable linear memory. While this model is well suited for …
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A shared-memory multiprocessor system using the raw tiled architecture
… the flexibility of this scheme, I implement a shared memory system on Raw, a tiled multiprocessor. A traditional directory-based cache coherence system is used. The directories are fully resident on several tiles, and the remaining tiles act as users, with cache maintenance routines accessed …
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Distributed shared memory for virtual environments
… to program, by designing a suitable distributed shared memory system. To be usable, the system must keep latency to a minimum, as virtual environments are very sensitive to it. The resulting design is push-based and non-consistent. Another requirement is that the system should be scaleable, over …
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Lower bounds in distributed computing
… problem, in which a set of processes in a shared memory system compete for exclusive access to a shared resource. We prove a tight Q(n log n) lower bound on the time for n processes to each access the resource once. .
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Modular verification of hardware systems
As hardware systems are becoming bigger and more complex, it is becoming increasingly harder to design and reason about these systems in a monolithic fashion. While hardware is often designed in a modular manner, its verification is rarely performed modularly. Moreover, any modular refinement to an …
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Optimizing high locality memory references in cache coherent shared memory multi-core processors
Optimizing memory references has been a primary research area of computer systems ever since the advent of the stored program computers. The objective of this thesis research is to identify and optimize two classes of high locality data memory reference streams in cache coherent shared memory …
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Distributed mobile platforms and applications for intelligent transportation systems
… a client-server programming model, sending all shared data queries and uploads through the cellular network, incurring bandwidth consumption and unpredictable latencies. Leveraging the local compute power and device-to-device communications of modern smartphones can mitigate demand on cellular …
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Verification and Performance of the DeNovo cache coherence protocol
… for the predicted hundreds of cores per chip, shared memory programming languages and environments must evolve to enforce disciplined practices like ``determinism-by-default semantics'' and ban ``wild shared-memory behaviors'' like arbitrary data races and potential non-determinism everywhere. …
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Power grid verification and optimization
… in large size, which results in the runtime and memory bottleneck with traditional methods. In order to address these issues, we focus on developing efficient methods to perform power grid verification and optimization. There are three topics related to power grid verification. Based on the …