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Showing 1 to 11 of 11 for “"Shallow trench isolation"”.
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Modeling of chemical mechanical polishing for shallow trench isolation
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
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Modeling of chemical mechanical polishing for shallow trench isolation
This thesis presents the nonlinear analysis, design, fabrication, and testing of an axial-gap magnetic induction micro machine, which is a two-phase planar motor in which the rotor is suspended above the stator via mechanical springs, or tethers. The micro motor is fabricated from thick layers of …
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Silicon/silicon Oxide Interface Roughness Studied by Scanning Tunneling Microscopy
… sample that has gone through a conventional shallow trench isolation process flow. We find that the autocovariance function has an exponential decay instead of a Gaussian decay. The corresponding electron and hole mobilities are measured and compared with the calculations of the mobilities …
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Modeling of advanced integrated circuit planarization processes : electrochemical-mechanical planarization (eCMP), STI CMP using non-conventional slurries
… ecient and accurate models for planarization of shallow-trench isolation (STI) structures are proposed, with a focus on die-scale and feature-scale uniformity. This thesis captures the fundamental weakness of CMP, pattern dependencies, and uses deposition prole effects as well as the …
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A test structure for the measurement and characterization of layout-induced transistor variation
… chosen in our design: polysilicon density and shallow-trench isolation (STI) density. A test structure is designed to study the systematic spatial dependency between transistors in order to determine the impact of different variation sources on transistor characteristics and understand the …
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A study of through-silicon-via (TSV) induced transistor variation
… and its interaction with polysilicon and shallow-trench-isolation (STI) layout pattern density. A test chip is designed with multiplexing test circuits providing measurements of key parameters of a large number of devices. These devices under test (DUTs) have layouts that explore a range …
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Metrology of SIMOX buried oxide and nitride/STI CMP
… The second system is the process, Nitride/Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP). CMP processes have been heralded as a way to planarize films and structures on wafers to a degree which has not been possible before. However, recent studies have shown that the …
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Modeling of chemical mechanical polishing for dielectric planarization
… dependencies in inter-level dielectric (ILD) and shallow trench isolation (STI) CMP, and develops a comprehensive semi-physically-based process model and characterization methodology. In the characterization phase, the planarization length of the process is determined. The planarization length is …
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Performance variations due to layout-dependent stress in VLSI circuits
… circuit delays in 3D-ICs. Thermal stresses from shallow trench isolation (STI) are another major source of unintentional stress that affect bulk planar transistors in conventional and 3D integrated circuits. STI is employed to electrically isolate transistors and the amount of STI surrounding an …
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Super-conformal coating and filling of high aspect ratio recessed structures by two-molecule CVD
… including MEMS devices, metallization and shallow trench isolation (STI) in integrated circuits. For structures with straight sidewalls, uniform coating methods – including chemical vapor deposition (CVD) or atomic layer deposition (ALD) – typically form a void or region of low density …
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Coating and filling of nanometer-scale structures using chemical vapor deposition
… aspect ratio (AR = 3 to 10) structures, such as trenches or vias, is necessary in nanoscale device fabrication. Examples include shallow trench isolation, metallization, and reverse tone patterning in integrated circuits and optical waveguides in photonic devices. Gas-phase coating methods such …