Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 14 of 14 for “"Serial links"”.
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IP Networks Over Heterogeneous Embedded Serial Links
… a variety of conventional and unconventional links. Interstice exposes a reprogrammable, dynamically-updatable packet-forwarding strategy, enabling forwarder nodes in principle to act as hubs, bridges, full routers, or implement firewalls or NAT, as application requirements and platform …
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Design and implementation of a phase locked loop for high-speed serial links
The student, Rushabh Mehta, accepted the attached license on 2016-04-25 at 13:40.
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Architectural & circuit level techniques to improve energy efficiency of high speed serial links
… on improving energy efficiency of communication links by exploring design techniques at both the architectural and circuit levels. In the first part of this work, we propose a time-based equalization scheme to implement transmit de-emphasis in voltage-mode output drivers. Using two-level …
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Asynchronous data-dependent jitter compensation
… the bit rates that can be achieved reliably over serial links. This thesis explains the causes of DDJ and existing equalization techniques, then develops an asynchronous (clock-agnostic) architecture for DDJ compensation. The compensation circuit alters the transition times of a digital signal to …
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Energy-efficient systems for information transfer and processing
… converter (ADC)-based multi-Gb/s serial link receivers, the power dissipation is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion-ratio (SNDR) and effective-number-of-bits (ENOB) as performance metrics because these are the standard for generic ADC …
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Toward realizing power scalable and energy proportional high-speed wireline links
… of cloud computing has placed high-speed serial links at the center stage. Due to saturating energy efficiency improvements over the last five years, increasing the data throughput comes at the cost of power consumption. Conventionally, serial link power can be reduced by optimizing …
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Design of fully digital inductors for low bandwidth filter applications
… and understood in the fields of clocking and serial links and applies it to analog circuit design. By using a ring oscillator to integrate the input voltage and a switched transconductor to inject current into the input node, the proposed time-domain gyrator achieves inductive input impedance …
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Design of energy-efficient high-speed wireline transceiver
… the need for energy-efficient high-speed I/O serial links. However, the rate at which the energy efficiency of serial links is improving is much slower than the rate at which the required data transfer bandwidth is increasing. This dissertation explores two design approaches for …
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Model predictive control equalization for high-speed IO links
… higher quantity and quality of information. Serial links provide a suitable architecture for this kind of transmission, because of speed, power and area limitations on parallel links. However, due to inter-symbol interference (ISI) and channel discontinuities, the data rate is being limited. …
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Circuit architectures for high speed CMOS clock and data recovery circuits
… a major impediment to increasing data rates in a serial communication system. Several CDR architectures have been proposed to ensure that the performance is comparable to traditional discrete SiGe, InP devices. In this thesis, three different CDR circuit architectures are designed in a 180 nm CMOS …
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Low-complexity coherent optical receivers
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-12-01
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Design of a phase locked loop based clocking circuit for high speed serial link applications
… need to scale accordingly and clever I/O links need to be developed. The most crucial component of any high-speed I/O link is the clocking circuitry: clock generator at the transmit (TX) end and clock-recovery unit on the receive (RX) end. This thesis provides an in-depth tutorial on …
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Digital enhancement techniques for fractional-N frequency synthesizers
… to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the …
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Clock multiplication techniques for high-speed I/Os
Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by …