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Showing 1 to 2 of 2 for “"Serial I/O"”.

  1. Design and ESD Protection of Wideband, Radio Frequency Integrated Circuits in CMOS Technologies

    … with a summary of the design of a 6.25-Gb/s serial I/O transceiver for backplane communications that implements error correction coding to reduce equalization power and transmitter output swing. The design of the transmit driver with pre-emphasis equalization, receiver amplifier, and voltage …

    uiuc Repository record for Design and ESD Protection of Wideband, Radio Frequency Integrated Circuits in CMOS Technologies (opens in a new tab)

  2. The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption

    … In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are converted into …

    uiuc Repository record for The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption (opens in a new tab)