Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 19 of 19 for “"Sequential Consistency"”.
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Techniques for low overhead fences and sequential consistency violation recording
… seeks to reduce the fence overhead in relaxed-consistency machines. It first introduces the WeeFence, a fence that is very cheap because it allows post-fence accesses to skip it. Such accesses can typically complete and retire before the pre-fence writes have drained from the write buffer. Only …
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Compilation Techniques for Explicitly Parallel Programs
… By doing this, we guarantee the correctness (sequential consistency) of the optimized program and maintain single processor performance in a multiprocessor environment. We also describe a parallel loop overhead reduction technique.
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Effective architectural support for detecting concurrency bugs
… namely data races, atomicity violations, and sequential consistency violations. Specifically, we propose novel, effective and efficient hardware-based techniques that help detect and isolate these bugs. We use hardware-based solutions because they lead to low overhead solutions. Therefore we …
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The dependence analysis and synchronization of parallel programs
… performed by the compiler are to preserve sequential consistency. Shasha and Snir investigated the problem for straight-line code with data accesses performed on scalars. We extend their results to programs with sequential loops and cobegin or doall loop parallelism and data accesses …
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Modular verification of hardware systems
… we prove that the combined system implements sequential consistency. To our knowledge, our memory-system proof is the first machine verification of a cache-coherence protocol parameterized over an arbitrary cache hierarchy, and our full-system proof is the first machine verification of …
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Optimizing directory-based cache coherence on the RAW architecture
… coherence protocols are necessary to ensure sequential consistency. Of the multiple coherence protocols developed, the scalability of directory-based schemes makes them ideal for RAW's architecture [1]. Although one such system has been demonstrated as a proof-of-concept, it lacks the ability …
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Memory consistency models for high performance distributed computing
… a mathematical framework for specifying the consistency guarantees of high performance distributed shared memory multiprocessors. This framework is based on computations, which specify the operations requested and constraints on how these operations may be applied; we call the framework …
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A verification framework suitable for proving large language translations
… in the language under the assumption of sequential consistency. Based on the Morpheus specification language, we extend the verification framework to prove the compiler translation semantic preservation property in a large real-world programming language with a real-world weak concurrency …
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The Semantics of Multicopy Atomic ARMv8 and RISC-V
… all memory accesses, with respect to notions of Sequential Consistency for mixed-size programs. During the course of this PhD project, and partly due to our extended collaboration with ARM, ARM have shifted to a much simplified multicopy-atomic concurrency architecture that also includes a formal …
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Views and consistencies in distributed shared memory
… DSM often suffers from performance problems as consistency requirements often incur long access latencies that cannot be overlapped with other operations in a process. Sequential consistency is the most general consistency requirement for DSM systems. This thesis explores two different avenues …
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Studies on memory consistency and synchronization : failure detection in parallel programs
… of shared memory parallel programs: memory consistency and techniques to detect synchronization failure in parallel programs. Overlapping execution of operations from a thread is an efficient way to effectively tolerate memory latency in shared memory multiprocessor systems. for a programmer …
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Memory abstractions for parallel programming
… that implement memory models weaker than sequential consistency, programs communicating via shared memory must employ memory-fences to ensure correct execution. This dissertation examines the concept of location-based memoryfences, which unlike traditional memory fences, incurs latency …
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Contributions to solvency risk measurement
… The first paper (Chapter 2) investigates time-consistency, the relation that should hold across risk measurements of the same financial position at different time points. Sufficient conditions are provided for coherent risk measures, in order to satisfy the requirements of acceptance-, …
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SNIC-DSM: SmartNIC based DSM Infrastructure for Heterogeneous-ISA Machines
… allows the implementation of different memory consistency protocols. Our experimental studies using compute-intensive benchmarks reveal that SNIC-DSM outperforms the state-of-the-art DSM - Popcorn Linux's software DSM - when server resource congestion is high.
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Specialization without complexity in heterogeneous memory systems
… such as GPUs means that coherence and consistency strategies designed for CPUs are ineffective, and evaluating the performance of alternative strategies is difficult. Recent efforts to implement coherence for such devices involve a simple software-driven coherence strategy combined with …
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f-DSM: An FPGA-Accelerated Distributed Shared Memory for Heterogeneous Instruction-Set-Architecture Hardware
… the flexibility to experiment with different DSM consistency protocols. This thesis presents fDSM, an FPGA-accelerated DSM framework for ISA-heterogeneous hardware. fDSM implements a high-speed messaging layer to enable inter-node communication across ISA-different CPU cores and a DSM protocol …
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Software and architecture support for the bulk multicore
… in programmability such as providing a sequentially consistent(SC) memory model, aiding atomicity violation detection, enabling deterministic reply, and even enabling deterministic execution. However, the implications of this chunking hardware on the compiler layer has not been studied …
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Record and deterministic replay of parallel programs on multiprocessors
… and Cyrus are limited in terms of the memory consistency models they support: Total Store Order (TSO) and Sequential Consistency (SC), respectively. To enable RnR for other architectures whose memory model is more relaxed, we then propose RelaxReplay. It is a general hardware-assisted MRR …
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Scalable and flexible bulk architecture
… Specifically, we focus on supporting Sequential Consistency (SC), a strong and intuitive memory consistency model. The first part of the thesis focuses on enforcing SC by chunk-based execution. I propose techniques to remove the scalability bottlenecks of chunk-based architectures. …