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Showing 1 to 3 of 3 for “"Self-Resetting logic"”.
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Low-swing signaling for energy efficient on-chip networks
… project, two clockless low-swing repeaters, a Self-Resetting Logic Repeater (SRLR) and a Voltage-Locked Repeater (VLR), have been proposed and analyzed in simulation only. They both require no reference clock, differential signaling, and bias current. Such digital-intensive properties enable …
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Towards low-power yet high-performance networks-on-chip
… of two clockless low-swing repeater designs, a self-resetting logic repeater (SRLR) optimized for transmission energy and a voltage-locked repeater (VLR) for transmission delay. This second chip prototype shows that the clockless, single-ended low-swing signaling of SRLRs armed with …
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Design And Synthesis Of Clockless Pipelines Based On Self-resetting Stage Logic
… relying on a clock signal to orchestrate logic operations across an entire chip became increasingly difficult. Motivated by this problem, designers are currently considering circuits which can operate without a clock. However, the wide acceptance of these circuits by the digital design …