Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 5 of 5 for “"Self Resetting"”.
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Synthesis Of Self-resetting Stage Logic Pipelines
… to avoid the global clocking problem. Recently, self-resetting circuits implemented in dynamic logic families have been proposed as viable clockless alternatives. While these circuits can produce excellent performances, they display serious limitations in terms of area cost and power consumption. …
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Design And Synthesis Of Clockless Pipelines Based On Self-resetting Stage Logic
… presents a new clockless technique, called self-resetting stage logic (SRSL), in which the computation of a block is reset periodically from within the block itself. SRSL is used as a building block for three coarse-grain pipelining techniques: (i) Stage-controlled self-resetting stage logic …
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Low-swing signaling for energy efficient on-chip networks
… project, two clockless low-swing repeaters, a Self-Resetting Logic Repeater (SRLR) and a Voltage-Locked Repeater (VLR), have been proposed and analyzed in simulation only. They both require no reference clock, differential signaling, and bias current. Such digital-intensive properties enable …
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Design of ultra low power analog-to-digital converter for ambulatory EEG recording
… every 16 clock cycle while being governed by a self-resetting SAR logic. The sampling rate can be scaled up to 32 kHz by varying the clock frequency to accommodate different number of channels used. The ADC was designed and fabricated in a 0.18 pm CMOS technology. The entire ADC core consumes 1 …
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Towards low-power yet high-performance networks-on-chip
… of two clockless low-swing repeater designs, a self-resetting logic repeater (SRLR) optimized for transmission energy and a voltage-locked repeater (VLR) for transmission delay. This second chip prototype shows that the clockless, single-ended low-swing signaling of SRLRs armed with …