Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 11 of 11 for “"Scratchpad"”.
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TIME-PREDICTABLE FAST MEMORIES: CACHES VS. SCRATCHPAD MEMORIES
… dissertation designs several time-predictable scratchpad memory (SPM) based architectures for both VLIW (Very Long InstructionWord) based single-core and multicore processors. First, this dissertation proposes a time predictable two-level SPM based architecture for VLIW based single-core …
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A real-time scratchpad-centric OS for multi-core embedded systems
… emerging approach is the integration of the scratchpad memory. Using scratchpad, at run time, the code and data for the requested task is made available in the scratchpad and contention can be avoided. In this thesis, we approach the problem of shared resource arbitration at an OS-level and …
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The Challenges of Non-linear Parameters and Variables in Automatic Loop Parallelisation
… we present a localisation technique to exploit scratchpad memories on architectures on which data caching has to be handled by software. We transform a given code such that it keeps values which are reused in successive iterations of a sequential loop in the scratchpad. An access to a value …
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Next-generation safety-critical systems on multi-core platforms
… architectural paradigms: cache-based and scratchpad-based platforms. On multi-core cache-based architectures, we design, implement and analyse a set of OS-level techniques that enforce hardware resource partitioning. In this context, we set two main goals. Our first objective is to achieve …
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Exploiting software information for an efficient memory hierarchy
… related to data storage. Caches and scratchpads are two popular organizations for storing data in today’s systems but they both have inefficiencies. Caches are power-hungry incurring expensive tag lookups and scratchpads incur unnecessary data movement as they are only locally …
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Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS
… multicore architectures into cache-based and scratchpad-based multicore platforms. For cache-based multicore architectures, the primary sources of contention among the cores include shared last-level cache (LLC), the DRAM memory controller, and the DRAM banks. Strict partitioning of shared …
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Energy-efficient mechanisms for managing on-chip storage in throughput processors
… the register file, GPUs also contain on-chip scratchpad memories and caches. Traditional systems have a fixed partitioning between these three structures. Applications have diverse requirements and often a single resource is most critical to performance. We propose to unify the register file, …
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Designing a Domain-Specific Accelerator for Graph Pattern Mining
… repetitive connectivity computation, an on-chip scratchpad is employed to memoize reusable intermediate results in the form of a connectivity map which enables fast vertex connectivity lookups. The proposed accelerator is implemented in a cycle-accurate simulator for performance evaluation. Key …
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Designing a Programmable Hardware Accelerator for Fully Homomorphic Encryption
… The compiler leverages F1's explicitly managed scratchpad to decouple computation from data movement, a necessary ingredient in achieving high performance given the large size of FHE operands. We evaluate F1 using cycle-accurate simulation and RTL synthesis. F1 is the first system to accelerate …
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Software instruction caching
… consists of a simple array memory (such as a scratchpad) and a software system that is capable of automatically managing that memory as a cache. Software caches have several advantages over traditional hardware caches. Without complex cache-management logic, the processor hardware is cheaper …
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Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy
… for such an environment, which can use scratchpads or incoherent caches, is challenging. Hence, this thesis focuses on architecting, programming, and evaluating an on-chip incoherent multiprocessor memory hierarchy. This thesis starts by examining incoherent multiprocessor caches. It …