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Showing 1 to 2 of 2 for “"Scrambling time to digital converter (TDC)"”.
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Techniques for low jitter clock multiplication
… significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a …
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Clock multiplication techniques for high-speed I/Os
… loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for …