Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 6 of 6 for “"Scan Chains"”.
-
Dynamic scan chains : a novel architecture to lower the cost of VLSI test
… thesis describes an architecture, named Dynamic Scan, that allows to reduce this cost by reducing the test data volume and, consequently, test application time. The Dynamic Scan architecture partitions the scan chains of the IC design into several segments by a set of multiplexers. The …
-
Design for Testability Techniques to Optimize VLSI Test Cost
… time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test data volume and test application time. …
-
METHODS TO MINIMIZE LINEAR DEPENDENCIES IN TWO-DIMENSIONAL SCAN DESIGNS
Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear …
-
New Techniques for Logic Built -in Self -Test
… One technique is the method of constrained scan cells. It overcomes the timing penalty of control points by enhancing controllability of CUT through scan path instead of functional path. By combining constrained scan cells with observation points in BIST implementation, BIST coverage …
-
Online Techniques for Enhancing the Diagnosis of Digital Circuits
… framework to the diagnosis of scan chains. In this method, we define a different metric that is applicable to scan chain diagnosis. Again, this method provides additional tests that are specific to the diagnosis of the particular scan chain defects in individual devices. We …
-
Testing and Security Related Considerations in Embedded Software
… ability to shift in data into and out of chip’s scan chains for test, the generic framework has allowed for its features to expand. For embedded microprocessor’s the interface allows for halting execution, insertion of instructions, reprogramming the software, and reading from memory. While it …