Global ETD Search
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Showing 1 to 11 of 11 for “"SRAM design"”.
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Scalable SRAM design
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
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Fault tolerant, low voltage SRAM design
… management a significant concern for circuit designers. Moreover, denser integration and shrinking geometries also have a negative impact on circuit reliability. Therefore, fault tolerance is becoming a more challenging problem. Static Random Access Memories (SRAMs) play a significant role in …
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Energy-efficient SRAM design in 28nm FDSOI Technology
… become more prominent. This is very critical in SRAMs, which use very small transistor dimensions to achieve high memory density. The conventional 6T SRAM bit-cell, which provides the smallest cell-area, fails to operate at lower supply voltages (Vdd). This is due to the significant degradation …
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Ultra-dynamic voltage scalable (U-DVS) SRAM design considerations
… pay significant attention to low-power circuit design for the past two decades. Operating digital circuits at lower voltage levels was shown to increase energy efficiency and lower power consumption. Being an integral part of the digital systems, Static Random Access Memories (SRAMs), dominate …
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Ultra-low-power SRAM design in high variability advanced CMOS
Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target …
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Efficient CNNs and Energy Efficient SRAM Design for ubiquitous medical devices
… energy efficient static random access memory (SRAM) with in-memory dot-product computation for low-power segmentation network implementation. The aim is to develop platform technology embodiments deployable across a wide range of health-monitoring wearable device applications requiring …
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Low-power and application-specific SRAM design for energy-efficient motion estimation
… critical than ever before for mobile devices. SRAMs are critical components in almost all SoCs affecting the overall energy-efficiency. This thesis focuses on algorithm and architecture development as well as low-power and application-specific SRAM design targeting motion estimation. First, a …
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Novel Non Precharging Single Bitline 8T Static Random Access Memory
Novel 8T SRAM design, employs individual bit-line (BL) and word-line (WL) for each operation. The read operation uses read word-line (RWL) and read bit-line (RBL) respectively. On other hand the write operation employs write word-line (WWL) and write bit line (WBL). Due to single BL and WL the …
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Low-voltage embedded biomedical processor design
… decreased quantization error over conventional designs. At the system level, the addition of accelerators increases leakage power and bus loading; strategies to mitigate these costs are analyzed in this thesis. A key strategy for improving energy efficiency is to aggressively scale the power …
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Energy-aware system design using circuit reconfigurability with a focus on low-power SRAMs
… complex systems generally target competing design goals such as maximizing performance while minimizing energy. Moreover, they have to work efficiently under changing system dynamics and application loads. Thus, for better power and performance optimization, they need to adapt to different …
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Non-Volatile Memory Adaptation in Asynchronous Microcontroller for Low Leakage Power and Fast Turn-on Time
… turn-on. This asynchronous non-volatile RAM is designed with a Spin-Transfer Torque (STT) memory device model and CMOS transistors in a 65 nm technology. A self-timed Quasi-Delay-Insensitive 1 KB STT RAM is designed with an MTNCL interface and handshaking protocol. A replica methodology is …