Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 21 for “"SOI-CMOS"”.
-
Study and development of low power consumption SRAMs on 28 nm FD-SOI CMOS process
Since analog circuit designs in CMOS nanometer (< 90 nm) nodes can be substantially affected by manufacturing process variations, circuit performance becomes more challenging to achieve efficient solutions by using analytical models. Extensive simulations are thus commonly required to provide a …
-
Low-swing signaling for energy efficient on-chip networks
… results of its test chip fabricated in 45nm SOI CMOS show that the tri-state RSD-based crossbar enables 55% power savings as compared to an equivalent full-swing crossbar and link. Also, the measurement results show that the proposed crossbar allows the broadcast-optimized on-chip networks …
-
Development of monolithic CMOS-compatible visible light emitting diode arrays on silicon
… synergies associated with integrating Si-based CMOS ICs and III-V-material-based light-emitting devices are very exciting and such integration has been an active area of research and development for quite some time now. SiGe virtual substrate technology presents one way to integrate these …
-
Asynchronous Circuit Stacking for Simplified Power Management
… problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm …
-
Wafer bonding for monolithic integration of Si CMOS VLSI electronics with III-V optoelectronic devices
… wafers are suitable for the fabrication of Si SOICMOS electronics and the subsequent monolithic integration of high performance optoelectronic devices. Future goals for this work include bonding fully processed SOI-CMOS wafers to the GaAs, rather than silicon wafers containing no electronics. …
-
Design of millimetre-wave input-reflectionless amplifiers in 45nm CMOS-SOI Technology
… implemented using 45-nm silicon-on-insulator (SOI) CMOS technology. The first design is a single-stage narrowband amplifier. The DC-power consumption of the designed amplifier is 5.3 mW. It has a peak gain of 5.3 dB at 31 GHz. The input-power-matching levels of the designed amplifier are better …
-
Amplitude and phase modulation techniques for an asymmetric multi-level outphasing transmitter
… as part of a complete transmitter in 45nm SOI CMOS utilizing four discrete power supplies and achieving data rates of up to 4GS/s. The design includes analysis and simulation of the control signal data path requirements for optimal system operation as well as switch optimization and effects …
-
Optical receiver techniques for integrated photonic links
… in a zero-foundry-change, commercial SOI CMOS logic process, and the first-ever monolithically-integrated optical receiver in a bulk CMOS memory process as part of a 9x5Gb/s DWDM receiver bank.
-
A high-speed, low-power analog-to-digital converter in fully depleted silicon-on-insulator technology
… in a fully depleted silicon-on-insulator CMOS technology. Silicon-on-insulator CMOS technology provides a number of benefits for low-power low-voltage analog design. The full dielectric isolation of the silicon island, where the transistors are built,allows higher layout packing density …
-
Energy efficient reconfigurable SRAM using data-dependency
… is implemented in a test chip using a 28nm FD-SOI CMOS process. Using post-layout simulations, the proposed SRAM is found to provide 14%-20%, 4%, and 31% reductions in read power as compared with a conventional 8T SRAM for three targeted applications: the coefficient SRAMs in a sparse Fast …
-
Monolithic electronic-photonic integration in state-of-the-art CMOS processes
As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior …
-
Efficiency enhancement techniques for RF and millimeter wave power amplifiers
… of their bias conditions. A Class E tuned CMOS power amplifier (PA) operating in the 60 GHz band was designed. Design, layout, and parasitic modeling considerations to attain high-efficiency millimeter-wave PA operation are discussed. Both single-ended and differential versions of the …
-
Flexible Mems: A Novel Technology To Fabricate Flexible Sensors And Electronics
… Systems) devices.</p> <p> MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro …
-
Characterization of process variability and robust optimization of analog circuits
Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm …
-
Wafer bonding of processed Si CMOS VLSI and GaAs for mixed technology integration
The successful bonding of bare thinned Si SOI wafers to bare GaAs wafers in previous research has proven to be an important first step in achieving integration of Si electronics with GaAs optoelectronic devices. The thinning of the SOI wafer has been shown to be a successful solution to the problem …
-
Circuit design for embedded memory in low-power integrated circuits
… with a 512kb 8T SRAM test chip in 45nm SOI CMOS technology. For active operation, an AC coupled sense amplifier and regenerative global bitline scheme are designed to operate at the limit of on current and off current separation on a single-ended SRAM bitline. The SRAM operates from 1.2 …
-
Reconfigurable Discrete-time Analog FIR filters for Wideband Analog Signal Processing
… provides robustness in the presence of digital CMOS scaling. The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. …
-
Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies
… reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, …
-
Device design and process technology for sub-100 nm SOI MOSFET's
Silicon-on-insulator (SOI) MOSFET's are an attractive alternative to bulk-silicon MOSFET's in the sub-100 nm gate length regime due to improved performance and/or scalability. The SOI layer thickness in SOI MOSFET's can be sized so that the channel is either partially- or fully-depleted-of majority …
Page 1 of 2