Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 10 of 10 for “"SERDES"”.
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High-Speed Low-Voltage Line Driver for SerDes Applications
… specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device …
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A high speed serializer/deserializer design
<p>A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in …
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Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures
… communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, …
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Machine learning approach for high speed link modeling and IBIS-AMI model generation
… model into IBIS-AMI, an industrial standard for SerDes simulation and verification. We started with developing a Volterra series model by extracting the Volterra kernels using feed forward neural networks. We proposed a monomial power series neural network (MPSNN) which can extract Volterra …
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Systems and circuits for broadband contactless and wireline transceivers
… multiplication in dense multi-lane high-speed SerDes. To avoid the challenges associated with directly synthesizing a high frequency clock using a phase-locked loop (PLL), the clock generator is built by a cascade of a ring-oscillator-based PLL and an open loop quadrupler. A sub-sampling error …
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High-swing PAM4 electrical transmitter with clock data recovery based timing error correction
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01
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Low-complexity coherent optical receivers
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-12-01
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High-performance die-to-die interconnects
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-12-01
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Equalization in continuous and discrete time for high speed links using 65 nm technology
"With the rapid growth of technology in areas such as the internet-of-things (IOT), network infrastructure, big data, etc., there has grown a need for low power and low cost integrated solutions in order to meet the specifications of these larger scale systems. Currently, many semiconductor …
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System-level design, simulation and measurement for high-speed data links
The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the …